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Vladimir Zapolskiy authored
In common clock framework CLK_DIVIDER_ONE_BASED or'ed with CLK_DIVIDER_ALLOW_ZERO flags indicates that 1) a divider clock may be set to zero value, 2) divider's zero value is interpreted as a non-divided clock. On the LPC32xx platform clock dividers of PWM and memory card clocks comply with the first condition, but zero value means a gated clock, thus it may happen that the divider value is not updated when the clock is enabled and the clock remains gated. The change adds one-shot quirks, which check for zero value of divider on initialization and set it to a non-zero value, therefore in runtime a gate clock will work as expected. Signed-off-by:
Vladimir Zapolskiy <vz@mleia.com> Reviewed-by:
Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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