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  • Kirill Smelkov
  • linux
  • Repository
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  • linux
  • drivers
  • gpu
  • drm
  • i915
  • intel_ringbuffer.c
Find file BlameHistoryPermalink
  • Ville Syrjälä's avatar
    drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ · b9e1faa7
    Ville Syrjälä authored Feb 14, 2013
    
    
    The bit controlling whether PIPE_CONTROL DW/QW write targets
    the global GTT or PPGTT moved moved from DW 2 bit 2 to
    DW 1 bit 24 on IVB.
    
    I verified on IVB that the fix is in fact effective. Without the fix
    none of the scratch writes actually landed in the pipe control page.
    With the fix the writes show up correctly.
    
    v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
    
    Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
    Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
    Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
    b9e1faa7
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