• Grygorii Strashko's avatar
    net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode · bc8d62e1
    Grygorii Strashko authored
    This patch adds MQPRIO Qdisc offload in full 'channel' mode which allows
    not only setting up pri:tc mapping, but also configuring TX shapers
    (rate-limiting) on external port FIFOs.
    
    The MQPRIO Qdisc offload is expected to work with or without VLAN/priority
    tagged packets.
    
    The CPSW external Port FIFO has 8 Priority queues. The rate-limit can be
    set for each of these priority queues. Which Priority queue a packet is
    assigned to depends on PN_REG_TX_PRI_MAP register which maps header
    priority to switch priority.
    
    The header priority of a packet is assigned via the RX_PRI_MAP_REG which
    maps packet priority to header priority.
    
    The packet priority is either the VLAN priority (for VLAN tagged packets)
    or the thread/channel offset.
    
    For simplicity, we assign the same priority queue to all queues of a
    Traffic Class so it can be rate-limited correctly.
    
    Configuration example:
     ethtool -L eth1 tx 5
     ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off
    
     tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \
     map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
     queues 1@0 1@1 1@2 hw 1 mode channel \
     shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit
    
     tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \
     map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1
    
     ip link add link eth1 name eth1.100 type vlan id 100
     ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7
    
    In the above example two ports share the same TX CPPI queue 0 for low
    priority traffic. 3 traffic classes are defined for eth1 and mapped to:
    TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit
    TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s
    TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s
    Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
    Signed-off-by: default avatarRoger Quadros <rogerq@kernel.org>
    Reviewed-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    bc8d62e1
am65-cpsw-qos.c 29.7 KB