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Thierry Reding authored
The memory controller on Tegra124 and later supports 34 or more address bits. Advertise that by setting the DMA mask based on the number of the address bits. Signed-off-by:Thierry Reding <treding@nvidia.com>
c4c21f22
The memory controller on Tegra124 and later supports 34 or more address
bits. Advertise that by setting the DMA mask based on the number of the
address bits.
Signed-off-by: Thierry Reding <treding@nvidia.com>