• Maciej Fijalkowski's avatar
    ice: Prepare legacy-rx for upcoming XDP multi-buffer support · c61bcebd
    Maciej Fijalkowski authored
    Rx path is going to be modified in a way that fragmented frame will be
    gathered within xdp_buff in the first place. This approach implies that
    underlying buffer has to provide tailroom for skb_shared_info. This is
    currently the case when ring uses build_skb but not when legacy-rx knob
    is turned on. This case configures 2k Rx buffers and has no way to
    provide either headroom or tailroom - FWIW it currently has
    XDP_PACKET_HEADROOM which is broken and in here it is removed. 2k Rx
    buffers were used so driver in this setting was able to support 9k MTU
    as it can chain up to 5 Rx buffers. With offset configuring HW writing
    2k of a data was passing the half of the page which broke the assumption
    of our internal page recycling tricks.
    
    Now if above got fixed and legacy-rx path would be left as is, when
    referring to skb_shared_info via xdp_get_shared_info_from_buff(),
    packet's content would be corrupted again. Hence size of Rx buffer needs
    to be lowered and therefore supported MTU. This operation will allow us
    to keep the unified data path and with 8k MTU users (if any of
    legacy-rx) would still be good to go. However, tendency is to drop the
    support for this code path at some point.
    
    Add ICE_RXBUF_1664 as vsi::rx_buf_len and ICE_MAX_FRAME_LEGACY_RX (8320)
    as vsi::max_frame for legacy-rx. For bigger page sizes configure 3k Rx
    buffers, not 2k.
    
    Since headroom support is removed, disable data_meta support on legacy-rx.
    When preparing XDP buff, rely on ice_rx_ring::rx_offset setting when
    deciding whether to support data_meta or not.
    Signed-off-by: default avatarMaciej Fijalkowski <maciej.fijalkowski@intel.com>
    Signed-off-by: default avatarDaniel Borkmann <daniel@iogearbox.net>
    Reviewed-by: default avatarAlexander Lobakin <alexandr.lobakin@intel.com>
    Link: https://lore.kernel.org/bpf/20230131204506.219292-2-maciej.fijalkowski@intel.com
    c61bcebd
ice_base.c 27.7 KB