• Peng Fan's avatar
    arm64: dts: imx8m: add cache info · cb551b5e
    Peng Fan authored
    i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache.
     - Icache is 2-way set associative
     - Dcache is 4-way set associative
     - L2cache is 16-way set associative
     - Line size are 64bytes
    
    Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache.
    
    So add the cache info in device tree and let use could see that
    from /sys/devices/system/cpu/cpu[x]/cache/
    Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
    Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
    cb551b5e
imx8mq.dtsi 45.7 KB