• Paul Mackerras's avatar
    perfcounters/powerpc: Make exclude_kernel bit work on Apple G5 processors · d095cd46
    Paul Mackerras authored
    Currently, setting hw_event.exclude_kernel does nothing on the PPC970
    variants used in Apple G5 machines, because they have the HV (hypervisor)
    bit in the MSR forced to 1, so as far as the PMU is concerned, the
    kernel runs in hypervisor mode.  Thus we have to use the MMCR0_FCHV
    (freeze counters in hypervisor mode) bit rather than the MMCR0_FCS
    (freeze counters in supervisor mode) bit.
    
    This checks the MSR.HV bit at startup, and if it is set, we set the
    freeze_counters_kernel variable to MMCR0_FCHV (it was initialized to
    MMCR0_FCS).  We then use that whenever we need to exclude kernel events.
    Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
    d095cd46
perf_counter.c 20.4 KB