• Fabio Estevam's avatar
    ASoC: sgtl5000: Remove MCLK restriction · d819ce96
    Fabio Estevam authored
    According to the sgtl5000 datasheet the MCLK frequency range restriction of
    8 to 27 MHz only applies when the PLL is used - synchronous SYS_MCLK input mode.
    
    When running the codec as slave, the master should generate MCLK in the range of
    256*fs, 384*fs or 512*fs, which is called asynchronous SYS_MCLK input mode.
    
    In asynchronous SYS_MCLK we cannot have the 8 to 27 MHz check because if we
    want to play a 8KHz sample rate track, with a MCLK of 8k * 512 = 4.096MHz the
    current check would return -EINVAL, which is not correct.
    
    Remove the 8 to 27MHz frequency check, since this only applies to the
    synchronous SYS_MCLK input case.
    Signed-off-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
    Signed-off-by: default avatarMark Brown <broonie@kernel.org>
    d819ce96
sgtl5000.c 40.1 KB