If the STEP (the interface between MAC and PHY) is in URM
(a lower speed mode) then we cannot use 320 MHz MCS > 9.
Therefore, limit the MCS in our capabilities in this case.
Note that this also limits the TX/rate scaling since that
takes both TX and RX capabilities into account.
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Reviewed-by: Gregory Greenman <gregory.greenman@intel.com>
Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
Link: https://msgid.link/20240123200528.02bae683b7fc.Id5efbb71d45da02c8c4e211d20396637ddd44da8@changeidSigned-off-by: Johannes Berg <johannes.berg@intel.com>