• Steve Capper's avatar
    arm64: mm: Logic to make offset_ttbr1 conditional · c812026c
    Steve Capper authored
    When running with a 52-bit userspace VA and a 48-bit kernel VA we offset
    ttbr1_el1 to allow the kernel pagetables with a 52-bit PTRS_PER_PGD to
    be used for both userspace and kernel.
    
    Moving on to a 52-bit kernel VA we no longer require this offset to
    ttbr1_el1 should we be running on a system with HW support for 52-bit
    VAs.
    
    This patch introduces conditional logic to offset_ttbr1 to query
    SYS_ID_AA64MMFR2_EL1 whenever 52-bit VAs are selected. If there is HW
    support for 52-bit VAs then the ttbr1 offset is skipped.
    
    We choose to read a system register rather than vabits_actual because
    offset_ttbr1 can be called in places where the kernel data is not
    actually mapped.
    
    Calls to offset_ttbr1 appear to be made from rarely called code paths so
    this extra logic is not expected to adversely affect performance.
    Signed-off-by: default avatarSteve Capper <steve.capper@arm.com>
    Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: default avatarWill Deacon <will@kernel.org>
    c812026c
hibernate-asm.S 4.75 KB