• Paul Mackerras's avatar
    [POWERPC] Use cache-inhibited large page bit from firmware · 84fdde5a
    Paul Mackerras authored
    Discussions with firmware architects have confirmed that the bit in
    the ibm,pa-features property that indicates support for
    cache-inhibited large (>= 64kB) page mappings does in fact mean that
    the hypervisor allows 64kB mappings to I/O devices.
    
    Thus we can now enable the code that tests that bit and sets our
    CPU_FTR_CI_LARGE_PAGE feature bit.
    Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
    84fdde5a
prom.c 36.1 KB