• Colin Xu's avatar
    drm/i915/gvt: Do not destroy ppgtt_mm during vGPU D3->D0. · ba25d977
    Colin Xu authored
    When system enters S3 state, device enters D3 state while RAM remains
    powered. From vGPU/GVT perspective, ppgtt_mm is residual in guest memory
    during vGPU in D3 state, so that when guest state transits from S3->S0,
    ppgtt_mm can be re-used and no need rebuild.
    
    Previous implementation invalidate and destroy ppgtt_mm at DMLR,
    regardless the power state transition is S0->S3->S0 (guest suspend or
    resume) or OFF->S0 (normal boot/reboot), invalidate and destroy ppgtt_mm
    is unnecessary in the former transition case.
    
    The patch saves the vGPU D3/D0 transition state when guest writes the
    PCI_PM_CTRL in vGPU's configure space, then in later DMLR, GVT can decide
    whether or not invalidate and destroy ppgtt_mm is required. The
    d3_entered flags is reset after DMLR.
    
    To test this feature, make sure S3 is enabled in QEMU parameters:
    i440fx: PIIX4_PM.disable_s3=0
    q35: ICH9-LPC.disable_s3=0
    Also need enable sleep option in guest OS if it's disabled.
    
    v2:
    - Revise commit message to more accurate description. (Kevin)
    - Split patch by logic. (Zhenyu)
    Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
    Signed-off-by: default avatarHang Yuan <hang.yuan@linux.intel.com>
    Signed-off-by: default avatarColin Xu <colin.xu@intel.com>
    Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/20200709071002.247960-2-colin.xu@intel.com
    ba25d977
gtt.c 74.4 KB