• Atish Patra's avatar
    RISC-V: Support cpu hotplug · f1e58583
    Atish Patra authored
    This patch enable support for cpu hotplug in RISC-V. It uses SBI HSM
    extension to online/offline any hart. As a result, the harts are
    returned to firmware once they are offline. If the harts are brought
    online afterwards, they re-enter Linux kernel as if a secondary hart
    booted for the first time. All booting requirements are honored during
    this process.
    
    Tested both on QEMU and HighFive Unleashed board with. Test result follows.
    
    ---------------------------------------------------
    Offline cpu 2
    ---------------------------------------------------
    $ echo 0 > /sys/devices/system/cpu/cpu2/online
    [   32.828684] CPU2: off
    $ cat /proc/cpuinfo
    processor       : 0
    hart            : 0
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 1
    hart            : 1
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 3
    hart            : 3
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 4
    hart            : 4
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 5
    hart            : 5
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 6
    hart            : 6
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 7
    hart            : 7
    isa             : rv64imafdcsu
    mmu             : sv48
    
    ---------------------------------------------------
    online cpu 2
    ---------------------------------------------------
    $ echo 1 > /sys/devices/system/cpu/cpu2/online
    $ cat /proc/cpuinfo
    processor       : 0
    hart            : 0
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 1
    hart            : 1
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 2
    hart            : 2
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 3
    hart            : 3
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 4
    hart            : 4
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 5
    hart            : 5
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 6
    hart            : 6
    isa             : rv64imafdcsu
    mmu             : sv48
    
    processor       : 7
    hart            : 7
    isa             : rv64imafdcsu
    mmu             : sv48
    Signed-off-by: default avatarAtish Patra <atish.patra@wdc.com>
    Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
    f1e58583
smp.h 2.02 KB