• Archit Taneja's avatar
    drm/msm/dsi: Add PHY/PLL for 8x96 · f079f6d9
    Archit Taneja authored
    Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL
    found on 8x96.
    
    These are picked up from the downstream driver. The PHY part is similar
    to the other DSI PHYs. The PLL driver requires some trickery so that
    one DSI PLL can drive both the DSIs (i.e, dual DSI mode).
    
    In the case of dual DSI mode. One DSI instance becomes the clock master,
    and other the clock slave. The master PLL's output (Byte and Pixel clock)
    is fed to both the DSI hosts/PHYs.
    
    When the DSIs are configured in dual DSI mode, the PHY driver communicates
    to the PLL driver using msm_dsi_pll_set_usecase() which instance is the
    master and which one is the slave. When setting rate, the master PLL also
    configures some of the slave PLL/PHY registers which need to be identical
    to the master's for correct dual DSI behaviour.
    
    There are 2 PLL post dividers that should have ideally been modelled as
    generic clk_divider clocks, but require some customization for dual DSI.
    In particular, when the master PLL's post-diviers are set, the slave PLL's
    post-dividers need to be set too. The clk_ops for these use clk_divider's
    helper ops and flags internally to prevent redundant code.
    
    Cc: Stephen Boyd <sboyd@codeaurora.org>
    Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
    Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
    f079f6d9
dsi_pll.c 3.65 KB