• Esben Haabendal's avatar
    net: ll_temac: Support indirect_mutex share within TEMAC IP · f14f5c11
    Esben Haabendal authored
    Indirect register access goes through a DCR bus bridge, which
    allows only one outstanding transaction.  And to make matters
    worse, each TEMAC IP block contains two Ethernet interfaces, and
    although they seem to have separate registers for indirect access,
    they actually share the registers.  Or to be more specific, MSW, LSW
    and CTL registers are physically shared between Ethernet interfaces
    in same TEMAC IP, with RDY register being (almost) specificic to
    the Ethernet interface.  The 0x10000 bit in RDY reflects combined
    bus ready state though.
    
    So we need to take care to synchronize not only within a single
    device, but also between devices in same TEMAC IP.
    
    This commit allows to do that with legacy platform devices.
    
    For OF devices, the xlnx,compound parent of the temac node should be
    used to find siblings, and setup a shared indirect_mutex between them.
    I will leave this work to somebody else, as I don't have hardware to
    test that.  No regression is introduced by that, as before this commit
    using two Ethernet interfaces in same TEMAC block is simply broken.
    Signed-off-by: default avatarEsben Haabendal <esben@geanix.com>
    Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
    Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
    f14f5c11
ll_temac.h 13.1 KB