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Chun-Jie Chen authored
In all MediaTek PLL design, bit0 of CON0 register is always the enable bit. However, there's a special case of usbpll on MT8192. The enable bit of usbpll is moved to bit2 of other register. Add configurable en_reg and pll_en_bit for enable control or default 0 where pll data are static variables. Hence, CON0_BASE_EN could also be removed. And there might have another special case on other chips, the enable bit is still on CON0 register but not at bit0. Reviewed-by:
Ikjoon Jang <ikjn@chromium.org> Signed-off-by:
Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by:
Chun-Jie Chen <chun-jie.chen@mediatek.com> Link: https://lore.kernel.org/r/20210726105719.15793-8-chun-jie.chen@mediatek.com Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
f384c447
