The DP spec says:
"If the receiver keeps the same value in the ADJUST_REQUEST_LANEx_y
 register(s) while the LANEx_CR_DONE bits remain unset, the transmitter
 must loop four times with the same voltage swing. On the fifth time,
 the transmitter must down-shift to the lower bit rate and must repeat
 the CR-lock training sequence as described below."

Lets fix the code to follow that instead of terminating after five
times of transmitting the same signal levels. The text in spec feels
a little bit ambiguous still, but this is my best guess at its meaning.

As a bonus this also gets rid of the train_set[0] stuff which
would not work for per-lane drive settings anyway.

Cc: Imre Deak <imre.deak@intel.com>
CC: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211001160826.17080-1-ville.syrjala@linux.intel.comReviewed-by: Imre Deak <imre.deak@intel.com>