• Atsushi Nemoto's avatar
    atmel_spi: fix clock polarity · f6febccd
    Atsushi Nemoto authored
    The atmel_spi driver does not initialize clock polarity correctly (except for
    at91rm9200 CS0 channel) in some case.
    
    The atmel_spi driver uses gpio-controlled chipselect.  OTOH spi clock signal
    is controlled by CSRn.CPOL bit, but this register controls clock signal
    correctly only in 'real transfer' duration.  At the time of cs_activate()
    call, CSRn.CPOL will be initialized correctly, but the controller do not know
    which channel is to be used next, so clock signal will stay at the inactive
    state of last transfer.  If clock polarity of new transfer and last transfer
    was differ, new transfer will start with wrong clock signal state.
    
    For example, if you started SPI MODE 2 or 3 transfer after SPI MODE 0 or 1
    transfer, the clock signal state at the assertion of chipselect will be low.
    Of course this will violates SPI transfer.
    
    This patch is short term solution for this problem.  It makes all CSRn.CPOL
    match for the transfer before activating chipselect.  For longer term, the
    best fix might be to let NPCS0 stay selected permanently in MR and overwrite
    CSR0 with to the new slave's settings before asserting CS.
    Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
    Acked-by: default avatarHaavard Skinnemoen <hskinnemoen@atmel.com>
    Cc: David Brownell <david-b@pacbell.net>
    Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
    Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
    f6febccd
atmel_spi.c 21.7 KB