• Florian Fainelli's avatar
    phy: brcm-sata: Correct MDIO operations for 40nm platforms · 0ed41b33
    Florian Fainelli authored
    The logic to write to MDIO registers on 40nm platforms was wrong
    because it would use the port number as an offset from the base address
    rather than the bank address of the PHY. This is hardly noticeable
    because the only programming we do is enabling SSC or not, which is not
    really causing an observable functional change.
    
    Correct that mistake by passing down the struct brcm_sata_port structure
    down to the brcm_sata_mdio_wr() and brcm_sata_mdio_rd() functions and do
    the proper offsetting for 28nm, respectively 40nm platforms from there.
    This means that brcm_sata_pcb_base() is now useless and is therefore
    removed.
    
    Fixes: c1602a1a ("phy: phy_brcmstb_sata: add support for MIPS-based platforms")
    Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
    Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
    0ed41b33
phy-brcm-sata.c 22.4 KB