The bcm570x chips provide a register that disables (masks) or enables
interrupts, and as a side effect, each write to this register regardless 
of value clears various PCI and internal interrupt-pending flags.  This
register, intr-mbox-0, provides a superset of the function provided
by the mask-pci-int and clear-pci-int bits in the misc-host-ctrl register.

Furthermore, the documentation clearly implies use of this register,
as an indicator that the host [tg3 driver] is in its interrupt handler.

The new tg3 logic, taking this knowledge into account, masks-and-clears
irqs using intr-mbox-0 [only] when a hard irq is received, and
unmasks-and-clears irqs at the end of tg3_poll after all NAPI events
have been exhausted.

The old logic twiddled the misc-host-ctrl irq masking bits separately
from intr-mbox-0 bits, which was not only inconsistent but also
a few additional I/Os that were not needed.