Add test case in automated tests suite. It checks not only the two types
of pmu event stytle formats "pmu_event_name" and "cpu/pmu_event_name/",
but also the different formats mixtures which are more likely to trigger
parse issue.

The patch set including this one has been tested by the perf automated
test:

   ./perf test parse -v"

On haswell, ivybridge and Romley platform.

The patch set also has been tested on haswell by the following script.

Note: please make sure that your test system support TSX and
L1-dcache-loads events. Otherwise, you may want to change the events to
other pmu events.

  [lk@localhost ~]$ cat perf_style_test.sh
  # hardware events + kernel pmu event with different style
  perf stat -x, -e cycles,mem-stores,tx-start sleep 2
  perf stat -x, -e cpu-cycles,cycles-ct,cycles-t sleep 2
  perf stat -x, -e cycles,cpu/cycles-ct/,cpu/cycles-t/ sleep 2
  perf stat -x, -e instructions,cpu/tx-start/ sleep 2
  perf stat -x, -e '{cycles,tx-start}' sleep 2
  perf stat -x, -e '{cycles,cpu/tx-start/}' sleep 2

  # HW Cache event + kernel pmu event with different style
  perf stat -x, -e L1-dcache-loads,cpu/mem-stores/,tx-start sleep 2
  perf stat -x, -e L1-dcache-loads,mem-stores,cpu/tx-start/ sleep 2
  perf stat -x, -e '{L1-dcache-loads,mem-stores}' sleep 2
  perf stat -x, -e '{L1-dcache-loads,cpu/tx-start/}' sleep 2

  # Raw event + kernel pmu event with different style:
  perf stat -x, -e cpu/event=0xc0,umask=0x00/,mem-loads,cpu/mem-stores/ sleep 2
  perf stat -x, -e cpu/event=0xc0,umask=0x00/,tx-start,cpu/el-start/ sleep 2
  perf stat -x, -e '{cpu/event=0xc0,umask=0x00/,tx-start}' sleep 2
Signed-off-by: Kan Liang <kan.liang@intel.com>
Acked-by: Jiri Olsa <jolsa@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Link: http://lkml.kernel.org/r/1412694532-23391-5-git-send-email-kan.liang@intel.comSigned-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>