drm/amd/display: remove dead display clock code

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h

@@ -44,7 +44,6 @@ struct display_clock_dce110 {
 	/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
 	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
 	uint32_t dfs_bypass_disp_clk;
-	struct display_clock_state clock_state;
 };
 
 #define DCLCK110_FROM_BASE(dc_base) \

drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h

@@ -45,7 +45,6 @@ struct display_clock_dce112 {
 	/* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
 	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
 	uint32_t dfs_bypass_disp_clk;
-	struct display_clock_state clock_state;
 	struct state_dependent_clocks *max_clks_by_state;
 
 };
@@ -75,17 +74,6 @@ bool dal_display_clock_dce112_construct(
 
 void dispclk_dce112_destroy(struct display_clock **base);
 
-uint32_t dispclk_dce112_calculate_min_clock(
-	struct display_clock *base,
-	uint32_t path_num,
-	struct min_clock_params *params);
-
-struct display_clock_state dispclk_dce112_get_clock_state(
-	struct display_clock *dc);
-
-uint32_t dispclk_dce112_get_dfs_bypass_threshold(
-	struct display_clock *dc);
-
 enum clocks_state dispclk_dce112_get_min_clocks_state(
 	struct display_clock *base);
 
@@ -93,16 +81,10 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
 	struct display_clock *dc,
 	struct state_dependent_clocks *req_clocks);
 
-uint32_t dispclk_dce112_get_validation_clock(struct display_clock *dc);
-
 void dispclk_dce112_set_clock(
 	struct display_clock *base,
 	uint32_t requested_clk_khz);
 
-void dispclk_dce112_set_clock_state(
-	struct display_clock *dc,
-	struct display_clock_state clk_state);
-
 bool dispclk_dce112_set_min_clocks_state(
 	struct display_clock *base,
 	enum clocks_state clocks_state);

drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h

@@ -48,7 +48,6 @@ struct display_clock_dce80 {
 	 * This is basically "Crystal Frequency In KHz" (XTALIN) frequency */
 	uint32_t dfs_bypass_disp_clk;
 	bool use_max_disp_clk;
-	struct display_clock_state clock_state;
 };
 
 struct display_clock *dal_display_clock_dce80_create(

drivers/gpu/drm/amd/display/dc/gpu/display_clock.c

@@ -26,49 +26,6 @@
 #include "dm_services.h"
 #include "display_clock.h"
 
-void dal_display_clock_base_set_dp_ref_clock_source(
-	struct display_clock *disp_clk,
-	enum clock_source_id clk_src)
-{/*must be implemented in derived*/
-
-}
-
-void dal_display_clock_base_set_clock_state(struct display_clock *disp_clk,
-	struct display_clock_state clk_state)
-{
-	/*Implemented only in DCE81*/
-}
-struct display_clock_state dal_display_clock_base_get_clock_state(
-	struct display_clock *disp_clk)
-{
-	/*Implemented only in DCE81*/
-	struct display_clock_state state = {0};
-	return state;
-}
-uint32_t dal_display_clock_base_get_dfs_bypass_threshold(
-	struct display_clock *disp_clk)
-{
-	/*Implemented only in DCE81*/
-	return 0;
-}
-
-bool dal_display_clock_construct_base(
-	struct display_clock *base,
-	struct dc_context *ctx)
-{
-	base->ctx = ctx;
-	base->id = CLOCK_SOURCE_ID_DCPLL;
-	base->min_display_clk_threshold_khz = 0;
-
-/* Initially set current min clocks state to invalid since we
- * cannot make any assumption about PPLIB's initial state. This will be updated
- * by HWSS via SetMinClocksState() on first mode set prior to programming
- * state dependent clocks.*/
-	base->cur_min_clks_state = CLOCKS_STATE_INVALID;
-
-	return true;
-}
-
 void dal_display_clock_destroy(struct display_clock **disp_clk)
 {
 	if (!disp_clk || !*disp_clk) {
@@ -81,26 +38,6 @@ void dal_display_clock_destroy(struct display_clock **disp_clk)
 	*disp_clk = NULL;
 }
 
-bool dal_display_clock_validate(
-	struct display_clock *disp_clk,
-	struct min_clock_params *params)
-{
-	return disp_clk->funcs->validate(disp_clk, params);
-}
-
-uint32_t dal_display_clock_calculate_min_clock(
-	struct display_clock *disp_clk,
-	uint32_t path_num,
-	struct min_clock_params *params)
-{
-	return disp_clk->funcs->calculate_min_clock(disp_clk, path_num, params);
-}
-
-uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk)
-{
-	return disp_clk->funcs->get_validation_clock(disp_clk);
-}
-
 void dal_display_clock_set_clock(
 	struct display_clock *disp_clk,
 	uint32_t requested_clock_khz)
@@ -108,11 +45,6 @@ void dal_display_clock_set_clock(
 	disp_clk->funcs->set_clock(disp_clk, requested_clock_khz);
 }
 
-uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk)
-{
-	return disp_clk->funcs->get_clock(disp_clk);
-}
-
 bool dal_display_clock_get_min_clocks_state(
 	struct display_clock *disp_clk,
 	enum clocks_state *clocks_state)
@@ -154,35 +86,6 @@ uint32_t dal_display_clock_get_dp_ref_clk_frequency(
 	return disp_clk->funcs->get_dp_ref_clk_frequency(disp_clk);
 }
 
-/*the second parameter of "switchreferenceclock" is
- * a dummy argument for all pre dce 6.0 versions*/
-
-void dal_display_clock_switch_reference_clock(
-	struct display_clock *disp_clk,
-	bool use_external_ref_clk,
-	uint32_t requested_clk_khz)
-{
-	/* TODO: requires Asic Control*/
-	/*
-	struct ac_pixel_clk_params params;
-	struct asic_control *ac =
-		dal_adapter_service_get_asic_control(disp_clk->as);
-	dc_service_memset(&params, 0, sizeof(struct ac_pixel_clk_params));
-
-	params.tgt_pixel_clk_khz = requested_clk_khz;
-	params.flags.SET_EXTERNAL_REF_DIV_SRC = use_external_ref_clk;
-	params.pll_id = disp_clk->id;
-	dal_asic_control_program_display_engine_pll(ac, &params);
-	*/
-}
-
-void dal_display_clock_set_dp_ref_clock_source(
-	struct display_clock *disp_clk,
-	enum clock_source_id clk_src)
-{
-	disp_clk->funcs->set_dp_ref_clock_source(disp_clk, clk_src);
-}
-
 void dal_display_clock_store_max_clocks_state(
 	struct display_clock *disp_clk,
 	enum clocks_state max_clocks_state)
@@ -190,28 +93,3 @@ void dal_display_clock_store_max_clocks_state(
 	disp_clk->funcs->store_max_clocks_state(disp_clk, max_clocks_state);
 }
 
-void dal_display_clock_set_clock_state(
-	struct display_clock *disp_clk,
-	struct display_clock_state clk_state)
-{
-	disp_clk->funcs->set_clock_state(disp_clk, clk_state);
-}
-
-struct display_clock_state dal_display_clock_get_clock_state(
-	struct display_clock *disp_clk)
-{
-	return disp_clk->funcs->get_clock_state(disp_clk);
-}
-
-uint32_t dal_display_clock_get_dfs_bypass_threshold(
-	struct display_clock *disp_clk)
-{
-	return disp_clk->funcs->get_dfs_bypass_threshold(disp_clk);
-}
-
-void dal_display_clock_invalid_clock_state(
-	struct display_clock *disp_clk)
-{
-	disp_clk->cur_min_clks_state = CLOCKS_STATE_INVALID;
-}
-

drivers/gpu/drm/amd/display/dc/gpu/display_clock.h

@@ -30,14 +30,8 @@
 
 struct display_clock_funcs {
 	void (*destroy)(struct display_clock **to_destroy);
-	bool (*validate)(struct display_clock *disp_clk,
-		struct min_clock_params *params);
-	uint32_t (*calculate_min_clock)(struct display_clock *disp_clk,
-		uint32_t path_num, struct min_clock_params *params);
-	uint32_t (*get_validation_clock)(struct display_clock *disp_clk);
 	void (*set_clock)(struct display_clock *disp_clk,
 		uint32_t requested_clock_khz);
-	uint32_t (*get_clock)(struct display_clock *disp_clk);
 	enum clocks_state (*get_min_clocks_state)(
 		struct display_clock *disp_clk);
 	enum clocks_state (*get_required_clocks_state)(
@@ -46,15 +40,8 @@ struct display_clock_funcs {
 	bool (*set_min_clocks_state)(struct display_clock *disp_clk,
 		enum clocks_state clocks_state);
 	uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
-	void (*set_dp_ref_clock_source)(struct display_clock *disp_clk,
-		enum clock_source_id clk_src);
 	void (*store_max_clocks_state)(struct display_clock *disp_clk,
 		enum clocks_state max_clocks_state);
-	void (*set_clock_state)(struct display_clock *disp_clk,
-		struct display_clock_state clk_state);
-	struct display_clock_state (*get_clock_state)(
-		struct display_clock *disp_clk);
-	uint32_t (*get_dfs_bypass_threshold)(struct display_clock *disp_clk);
 
 };
 
@@ -66,21 +53,6 @@ struct display_clock {
 
 	enum clocks_state cur_min_clks_state;
 };
-void dal_display_clock_base_set_dp_ref_clock_source(
-	struct display_clock *disp_clk,
-	enum clock_source_id clk_src);
-struct display_clock_state dal_display_clock_base_get_clock_state(
-	struct display_clock *disp_clk);
-uint32_t dal_display_clock_base_get_dfs_bypass_threshold(
-	struct display_clock *disp_clk);
-void dal_display_clock_base_set_clock_state(struct display_clock *disp_clk,
-	struct display_clock_state clk_state);
-bool dal_display_clock_construct_base(
-	struct display_clock *base,
-	struct dc_context *ctx);
-
-uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk);
-
 void dal_display_clock_store_max_clocks_state(
 	struct display_clock *disp_clk,
 	enum clocks_state max_clocks_state);

drivers/gpu/drm/amd/display/include/display_clock_interface.h

@@ -30,60 +30,6 @@
 #include "grph_object_defs.h"
 #include "signal_types.h"
 
-/* Timing related information*/
-struct dc_timing_params {
-	uint32_t INTERLACED:1;
-	uint32_t HCOUNT_BY_TWO:1;
-	uint32_t PIXEL_REPETITION:4; /*< values 1 to 10 supported*/
-	uint32_t PREFETCH:1;
-
-	uint32_t h_total;
-	uint32_t h_addressable;
-	uint32_t h_sync_width;
-};
-
-/* Scaling related information*/
-struct dc_scaling_params {
-	uint32_t h_overscan_right;
-	uint32_t h_overscan_left;
-	uint32_t h_taps;
-	uint32_t v_taps;
-};
-
-/* VScalerEfficiency */
-enum v_scaler_efficiency {
-	V_SCALER_EFFICIENCY_LB36BPP = 0,
-	V_SCALER_EFFICIENCY_LB30BPP = 1,
-	V_SCALER_EFFICIENCY_LB24BPP = 2,
-	V_SCALER_EFFICIENCY_LB18BPP = 3
-};
-
-/* Parameters required for minimum Engine
- * and minimum Display clock calculations*/
-struct min_clock_params {
-	uint32_t id;
-	uint32_t requested_pixel_clock; /* in KHz */
-	uint32_t actual_pixel_clock; /* in KHz */
-	struct view source_view;
-	struct view dest_view;
-	struct dc_timing_params timing_info;
-	struct dc_scaling_params scaling_info;
-	enum signal_type signal_type;
-	enum dc_color_depth deep_color_depth;
-	enum v_scaler_efficiency scaler_efficiency;
-	bool line_buffer_prefetch_enabled;
-};
-
-/* Result of Minimum System and Display clock calculations.
- * Minimum System clock and Display clock, source and path to be used
- * for Display clock*/
-struct minimum_clocks_calculation_result {
-	uint32_t min_sclk_khz;
-	uint32_t min_dclk_khz;
-	uint32_t min_mclk_khz;
-	uint32_t min_deep_sleep_sclk;
-};
-
 /* Enumeration of all clocks states */
 enum clocks_state {
 	CLOCKS_STATE_INVALID = 0,
@@ -110,10 +56,6 @@ struct state_dependent_clocks {
 	uint32_t pixel_clk_khz;
 };
 
-struct display_clock_state {
-	uint32_t DFS_BYPASS_ACTIVE:1;
-};
-
 struct display_clock;
 
 struct display_clock *dal_display_clock_dce112_create(
@@ -126,18 +68,9 @@ struct display_clock *dal_display_clock_dce80_create(
 	struct dc_context *ctx);
 
 void dal_display_clock_destroy(struct display_clock **to_destroy);
-bool dal_display_clock_validate(
-	struct display_clock *disp_clk,
-	struct min_clock_params *params);
-uint32_t dal_display_clock_calculate_min_clock(
-	struct display_clock *disp_clk,
-	uint32_t path_num,
-	struct min_clock_params *params);
-uint32_t dal_display_clock_get_validation_clock(struct display_clock *disp_clk);
 void dal_display_clock_set_clock(
 	struct display_clock *disp_clk,
 	uint32_t requested_clock_khz);
-uint32_t dal_display_clock_get_clock(struct display_clock *disp_clk);
 bool dal_display_clock_get_min_clocks_state(
 	struct display_clock *disp_clk,
 	enum clocks_state *clocks_state);
@@ -150,26 +83,8 @@ bool dal_display_clock_set_min_clocks_state(
 	enum clocks_state clocks_state);
 uint32_t dal_display_clock_get_dp_ref_clk_frequency(
 	struct display_clock *disp_clk);
-/*the second parameter of "switchreferenceclock" is
- * a dummy argument for all pre dce 6.0 versions*/
-void dal_display_clock_switch_reference_clock(
-	struct display_clock *disp_clk,
-	bool use_external_ref_clk,
-	uint32_t requested_clock_khz);
-void dal_display_clock_set_dp_ref_clock_source(
-	struct display_clock *disp_clk,
-	enum clock_source_id clk_src);
 void dal_display_clock_store_max_clocks_state(
 	struct display_clock *disp_clk,
 	enum clocks_state max_clocks_state);
-void dal_display_clock_set_clock_state(
-	struct display_clock *disp_clk,
-	struct display_clock_state clk_state);
-struct display_clock_state dal_display_clock_get_clock_state(
-	struct display_clock *disp_clk);
-uint32_t dal_display_clock_get_dfs_bypass_threshold(
-	struct display_clock *disp_clk);
-void dal_display_clock_invalid_clock_state(
-	struct display_clock *disp_clk);
 
 #endif /* __DISPLAY_CLOCK_INTERFACE_H__ */