Commit 00dfe298 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven

pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts

On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also
the pin configs are completely different. This patch makes sure we use the
appropriate pin configs for each SoC (which is passed as part of the OF
data) while configuring the GPIO pin as interrupts instead of using
rzg2l_gpio_configs[] for all the SoCs.

Fixes: bfc69bdb ("pinctrl: renesas: rzg2l: Add RZ/G2UL support")
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230102221815.273719-3-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 34cf9a85
...@@ -130,6 +130,7 @@ struct rzg2l_dedicated_configs { ...@@ -130,6 +130,7 @@ struct rzg2l_dedicated_configs {
struct rzg2l_pinctrl_data { struct rzg2l_pinctrl_data {
const char * const *port_pins; const char * const *port_pins;
const u32 *port_pin_configs; const u32 *port_pin_configs;
unsigned int n_ports;
struct rzg2l_dedicated_configs *dedicated_pins; struct rzg2l_dedicated_configs *dedicated_pins;
unsigned int n_port_pins; unsigned int n_port_pins;
unsigned int n_dedicated_pins; unsigned int n_dedicated_pins;
...@@ -1124,7 +1125,7 @@ static struct { ...@@ -1124,7 +1125,7 @@ static struct {
} }
}; };
static int rzg2l_gpio_get_gpioint(unsigned int virq) static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)
{ {
unsigned int gpioint; unsigned int gpioint;
unsigned int i; unsigned int i;
...@@ -1133,13 +1134,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq) ...@@ -1133,13 +1134,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq)
port = virq / 8; port = virq / 8;
bit = virq % 8; bit = virq % 8;
if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || if (port >= data->n_ports ||
bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
return -EINVAL; return -EINVAL;
gpioint = bit; gpioint = bit;
for (i = 0; i < port; i++) for (i = 0; i < port; i++)
gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
return gpioint; return gpioint;
} }
...@@ -1239,7 +1240,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, ...@@ -1239,7 +1240,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
unsigned long flags; unsigned long flags;
int gpioint, irq; int gpioint, irq;
gpioint = rzg2l_gpio_get_gpioint(child); gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);
if (gpioint < 0) if (gpioint < 0)
return gpioint; return gpioint;
...@@ -1313,8 +1314,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, ...@@ -1313,8 +1314,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
port = offset / 8; port = offset / 8;
bit = offset % 8; bit = offset % 8;
if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || if (port >= pctrl->data->n_ports ||
bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
clear_bit(offset, valid_mask); clear_bit(offset, valid_mask);
} }
} }
...@@ -1519,6 +1520,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) ...@@ -1519,6 +1520,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
static struct rzg2l_pinctrl_data r9a07g043_data = { static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names, .port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs, .port_pin_configs = r9a07g043_gpio_configs,
.n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common, .dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
...@@ -1527,6 +1529,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { ...@@ -1527,6 +1529,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
static struct rzg2l_pinctrl_data r9a07g044_data = { static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pins = rzg2l_gpio_names, .port_pins = rzg2l_gpio_names,
.port_pin_configs = rzg2l_gpio_configs, .port_pin_configs = rzg2l_gpio_configs,
.n_ports = ARRAY_SIZE(rzg2l_gpio_configs),
.dedicated_pins = rzg2l_dedicated_pins.common, .dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names),
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
......
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