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Commit 0296b5d9 authored by Alexandre Courbot's avatar Alexandre Courbot Committed by Ben Skeggs
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drm/nouveau/gr/gf100: split gf100_gr_init_ctxctl() 

gf100_gr_init_ctxctl() is basically two different functions (one for
use of internal firmware, the other for use of external firmware), but
its current layout makes it look more complex than it is. Split it to
better reflect that fact.
Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent d2753f40
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Showing with 115 additions and 97 deletions
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View file @ 0296b5d9
...@@ -1455,134 +1455,139 @@ gf100_gr_init_csdata(struct gf100_gr *gr, ...@@ -1455,134 +1455,139 @@ gf100_gr_init_csdata(struct gf100_gr *gr,
nvkm_wr32(device, falcon + 0x01c4, star + 4); nvkm_wr32(device, falcon + 0x01c4, star + 4);
} }
int /* Initialize context from an external (secure or not) firmware */
gf100_gr_init_ctxctl(struct gf100_gr *gr) static int
gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
{ {
const struct gf100_grctx_func *grctx = gr->func->grctx;
struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device; struct nvkm_device *device = subdev->device;
struct nvkm_secboot *sb = device->secboot; struct nvkm_secboot *sb = device->secboot;
int i;
int ret = 0; int ret = 0;
if (gr->firmware) { /* load fuc microcode */
/* load fuc microcode */ nvkm_mc_unk260(device, 0);
nvkm_mc_unk260(device, 0);
/* securely-managed falcons must be reset using secure boot */
if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS);
else
gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c,
&gr->fuc409d);
if (ret)
return ret;
if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS)) /* securely-managed falcons must be reset using secure boot */
ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS); if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
else ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS);
gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, else
&gr->fuc41ad); gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d);
if (ret) if (ret)
return ret; return ret;
nvkm_mc_unk260(device, 1); if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
ret = nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS);
/* start both of them running */ else
nvkm_wr32(device, 0x409840, 0xffffffff); gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad);
nvkm_wr32(device, 0x41a10c, 0x00000000); if (ret)
nvkm_wr32(device, 0x40910c, 0x00000000); return ret;
if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS);
else
nvkm_wr32(device, 0x41a100, 0x00000002);
if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS);
else
nvkm_wr32(device, 0x409100, 0x00000002);
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800) & 0x00000001)
break;
) < 0)
return -EBUSY;
nvkm_wr32(device, 0x409840, 0xffffffff); nvkm_mc_unk260(device, 1);
nvkm_wr32(device, 0x409500, 0x7fffffff);
nvkm_wr32(device, 0x409504, 0x00000021); /* start both of them running */
nvkm_wr32(device, 0x409840, 0xffffffff);
nvkm_wr32(device, 0x41a10c, 0x00000000);
nvkm_wr32(device, 0x40910c, 0x00000000);
nvkm_wr32(device, 0x409840, 0xffffffff); if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
nvkm_wr32(device, 0x409500, 0x00000000); nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS);
nvkm_wr32(device, 0x409504, 0x00000010); else
nvkm_wr32(device, 0x41a100, 0x00000002);
if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS);
else
nvkm_wr32(device, 0x409100, 0x00000002);
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800) & 0x00000001)
break;
) < 0)
return -EBUSY;
nvkm_wr32(device, 0x409840, 0xffffffff);
nvkm_wr32(device, 0x409500, 0x7fffffff);
nvkm_wr32(device, 0x409504, 0x00000021);
nvkm_wr32(device, 0x409840, 0xffffffff);
nvkm_wr32(device, 0x409500, 0x00000000);
nvkm_wr32(device, 0x409504, 0x00000010);
if (nvkm_msec(device, 2000,
if ((gr->size = nvkm_rd32(device, 0x409800)))
break;
) < 0)
return -EBUSY;
nvkm_wr32(device, 0x409840, 0xffffffff);
nvkm_wr32(device, 0x409500, 0x00000000);
nvkm_wr32(device, 0x409504, 0x00000016);
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800))
break;
) < 0)
return -EBUSY;
nvkm_wr32(device, 0x409840, 0xffffffff);
nvkm_wr32(device, 0x409500, 0x00000000);
nvkm_wr32(device, 0x409504, 0x00000025);
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800))
break;
) < 0)
return -EBUSY;
if (device->chipset >= 0xe0) {
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000030);
if (nvkm_msec(device, 2000, if (nvkm_msec(device, 2000,
if ((gr->size = nvkm_rd32(device, 0x409800))) if (nvkm_rd32(device, 0x409800))
break; break;
) < 0) ) < 0)
return -EBUSY; return -EBUSY;
nvkm_wr32(device, 0x409840, 0xffffffff); nvkm_wr32(device, 0x409810, 0xb00095c8);
nvkm_wr32(device, 0x409500, 0x00000000); nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409504, 0x00000016); nvkm_wr32(device, 0x409500, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000031);
if (nvkm_msec(device, 2000, if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800)) if (nvkm_rd32(device, 0x409800))
break; break;
) < 0) ) < 0)
return -EBUSY; return -EBUSY;
nvkm_wr32(device, 0x409840, 0xffffffff); nvkm_wr32(device, 0x409810, 0x00080420);
nvkm_wr32(device, 0x409500, 0x00000000); nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409504, 0x00000025); nvkm_wr32(device, 0x409500, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000032);
if (nvkm_msec(device, 2000, if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800)) if (nvkm_rd32(device, 0x409800))
break; break;
) < 0) ) < 0)
return -EBUSY; return -EBUSY;
if (device->chipset >= 0xe0) { nvkm_wr32(device, 0x409614, 0x00000070);
nvkm_wr32(device, 0x409800, 0x00000000); nvkm_wr32(device, 0x409614, 0x00000770);
nvkm_wr32(device, 0x409500, 0x00000001); nvkm_wr32(device, 0x40802c, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000030); }
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800))
break;
) < 0)
return -EBUSY;
nvkm_wr32(device, 0x409810, 0xb00095c8);
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000031);
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800))
break;
) < 0)
return -EBUSY;
nvkm_wr32(device, 0x409810, 0x00080420);
nvkm_wr32(device, 0x409800, 0x00000000);
nvkm_wr32(device, 0x409500, 0x00000001);
nvkm_wr32(device, 0x409504, 0x00000032);
if (nvkm_msec(device, 2000,
if (nvkm_rd32(device, 0x409800))
break;
) < 0)
return -EBUSY;
nvkm_wr32(device, 0x409614, 0x00000070); if (gr->data == NULL) {
nvkm_wr32(device, 0x409614, 0x00000770); int ret = gf100_grctx_generate(gr);
nvkm_wr32(device, 0x40802c, 0x00000001); if (ret) {
nvkm_error(subdev, "failed to construct context\n");
return ret;
} }
}
if (gr->data == NULL) { return 0;
int ret = gf100_grctx_generate(gr); }
if (ret) {
nvkm_error(subdev, "failed to construct context\n"); static int
return ret; gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
} {
} const struct gf100_grctx_func *grctx = gr->func->grctx;
struct nvkm_subdev *subdev = &gr->base.engine.subdev;
struct nvkm_device *device = subdev->device;
int i;
return 0;
} else
if (!gr->func->fecs.ucode) { if (!gr->func->fecs.ucode) {
return -ENOSYS; return -ENOSYS;
} }
...@@ -1642,6 +1647,19 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) ...@@ -1642,6 +1647,19 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr)
return 0; return 0;
} }
int
gf100_gr_init_ctxctl(struct gf100_gr *gr)
{
int ret;
if (gr->firmware)
ret = gf100_gr_init_ctxctl_ext(gr);
else
ret = gf100_gr_init_ctxctl_int(gr);
return ret;
}
static int static int
gf100_gr_oneinit(struct nvkm_gr *base) gf100_gr_oneinit(struct nvkm_gr *base)
{ {
......
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