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Commit 03751e79 authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
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MIPS: Code formatting fixes. 

Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 36be5051
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Showing with 40 additions and 40 deletions
arch/mips/kernel/cpu-probe.c
View file @ 03751e79
...@@ -340,7 +340,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -340,7 +340,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R2000"; __cpu_name[cpu] = "R2000";
c->isa_level = MIPS_CPU_ISA_I; c->isa_level = MIPS_CPU_ISA_I;
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
MIPS_CPU_NOFPUEX; MIPS_CPU_NOFPUEX;
if (__cpu_has_fpu()) if (__cpu_has_fpu())
c->options |= MIPS_CPU_FPU; c->options |= MIPS_CPU_FPU;
c->tlbsize = 64; c->tlbsize = 64;
...@@ -361,7 +361,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -361,7 +361,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
} }
c->isa_level = MIPS_CPU_ISA_I; c->isa_level = MIPS_CPU_ISA_I;
c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
MIPS_CPU_NOFPUEX; MIPS_CPU_NOFPUEX;
if (__cpu_has_fpu()) if (__cpu_has_fpu())
c->options |= MIPS_CPU_FPU; c->options |= MIPS_CPU_FPU;
c->tlbsize = 64; c->tlbsize = 64;
...@@ -387,8 +387,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -387,8 +387,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
c->isa_level = MIPS_CPU_ISA_III; c->isa_level = MIPS_CPU_ISA_III;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_WATCH | MIPS_CPU_VCE | MIPS_CPU_WATCH | MIPS_CPU_VCE |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 48; c->tlbsize = 48;
break; break;
case PRID_IMP_VR41XX: case PRID_IMP_VR41XX:
...@@ -434,7 +434,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -434,7 +434,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R4300"; __cpu_name[cpu] = "R4300";
c->isa_level = MIPS_CPU_ISA_III; c->isa_level = MIPS_CPU_ISA_III;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 32; c->tlbsize = 32;
break; break;
case PRID_IMP_R4600: case PRID_IMP_R4600:
...@@ -446,7 +446,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -446,7 +446,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
c->tlbsize = 48; c->tlbsize = 48;
break; break;
#if 0 #if 0
case PRID_IMP_R4650: case PRID_IMP_R4650:
/* /*
* This processor doesn't have an MMU, so it's not * This processor doesn't have an MMU, so it's not
* "real easy" to run Linux on it. It is left purely * "real easy" to run Linux on it. It is left purely
...@@ -455,9 +455,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -455,9 +455,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
*/ */
c->cputype = CPU_R4650; c->cputype = CPU_R4650;
__cpu_name[cpu] = "R4650"; __cpu_name[cpu] = "R4650";
c->isa_level = MIPS_CPU_ISA_III; c->isa_level = MIPS_CPU_ISA_III;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
c->tlbsize = 48; c->tlbsize = 48;
break; break;
#endif #endif
case PRID_IMP_TX39: case PRID_IMP_TX39:
...@@ -488,7 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -488,7 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R4700"; __cpu_name[cpu] = "R4700";
c->isa_level = MIPS_CPU_ISA_III; c->isa_level = MIPS_CPU_ISA_III;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 48; c->tlbsize = 48;
break; break;
case PRID_IMP_TX49: case PRID_IMP_TX49:
...@@ -505,7 +505,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -505,7 +505,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R5000"; __cpu_name[cpu] = "R5000";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 48; c->tlbsize = 48;
break; break;
case PRID_IMP_R5432: case PRID_IMP_R5432:
...@@ -513,7 +513,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -513,7 +513,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R5432"; __cpu_name[cpu] = "R5432";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_WATCH | MIPS_CPU_LLSC; MIPS_CPU_WATCH | MIPS_CPU_LLSC;
c->tlbsize = 48; c->tlbsize = 48;
break; break;
case PRID_IMP_R5500: case PRID_IMP_R5500:
...@@ -521,7 +521,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -521,7 +521,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R5500"; __cpu_name[cpu] = "R5500";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_WATCH | MIPS_CPU_LLSC; MIPS_CPU_WATCH | MIPS_CPU_LLSC;
c->tlbsize = 48; c->tlbsize = 48;
break; break;
case PRID_IMP_NEVADA: case PRID_IMP_NEVADA:
...@@ -529,7 +529,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -529,7 +529,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "Nevada"; __cpu_name[cpu] = "Nevada";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_DIVEC | MIPS_CPU_LLSC; MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
c->tlbsize = 48; c->tlbsize = 48;
break; break;
case PRID_IMP_R6000: case PRID_IMP_R6000:
...@@ -537,7 +537,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -537,7 +537,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R6000"; __cpu_name[cpu] = "R6000";
c->isa_level = MIPS_CPU_ISA_II; c->isa_level = MIPS_CPU_ISA_II;
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 32; c->tlbsize = 32;
break; break;
case PRID_IMP_R6000A: case PRID_IMP_R6000A:
...@@ -545,7 +545,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -545,7 +545,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R6000A"; __cpu_name[cpu] = "R6000A";
c->isa_level = MIPS_CPU_ISA_II; c->isa_level = MIPS_CPU_ISA_II;
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 32; c->tlbsize = 32;
break; break;
case PRID_IMP_RM7000: case PRID_IMP_RM7000:
...@@ -553,7 +553,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -553,7 +553,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "RM7000"; __cpu_name[cpu] = "RM7000";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
/* /*
* Undocumented RM7000: Bit 29 in the info register of * Undocumented RM7000: Bit 29 in the info register of
* the RM7000 v2.0 indicates if the TLB has 48 or 64 * the RM7000 v2.0 indicates if the TLB has 48 or 64
...@@ -569,7 +569,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -569,7 +569,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "RM9000"; __cpu_name[cpu] = "RM9000";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
/* /*
* Bit 29 in the info register of the RM9000 * Bit 29 in the info register of the RM9000
* indicates if the TLB has 48 or 64 entries. * indicates if the TLB has 48 or 64 entries.
...@@ -584,8 +584,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -584,8 +584,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "RM8000"; __cpu_name[cpu] = "RM8000";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
break; break;
case PRID_IMP_R10000: case PRID_IMP_R10000:
...@@ -593,9 +593,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -593,9 +593,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R10000"; __cpu_name[cpu] = "R10000";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 64; c->tlbsize = 64;
break; break;
case PRID_IMP_R12000: case PRID_IMP_R12000:
...@@ -603,9 +603,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -603,9 +603,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R12000"; __cpu_name[cpu] = "R12000";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 64; c->tlbsize = 64;
break; break;
case PRID_IMP_R14000: case PRID_IMP_R14000:
...@@ -613,9 +613,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) ...@@ -613,9 +613,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "R14000"; __cpu_name[cpu] = "R14000";
c->isa_level = MIPS_CPU_ISA_IV; c->isa_level = MIPS_CPU_ISA_IV;
c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_FPU | MIPS_CPU_32FPR |
MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
MIPS_CPU_LLSC; MIPS_CPU_LLSC;
c->tlbsize = 64; c->tlbsize = 64;
break; break;
case PRID_IMP_LOONGSON2: case PRID_IMP_LOONGSON2:
...@@ -739,7 +739,7 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) ...@@ -739,7 +739,7 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
if (config3 & MIPS_CONF3_VEIC) if (config3 & MIPS_CONF3_VEIC)
c->options |= MIPS_CPU_VEIC; c->options |= MIPS_CPU_VEIC;
if (config3 & MIPS_CONF3_MT) if (config3 & MIPS_CONF3_MT)
c->ases |= MIPS_ASE_MIPSMT; c->ases |= MIPS_ASE_MIPSMT;
if (config3 & MIPS_CONF3_ULRI) if (config3 & MIPS_CONF3_ULRI)
c->options |= MIPS_CPU_ULRI; c->options |= MIPS_CPU_ULRI;
...@@ -767,7 +767,7 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) ...@@ -767,7 +767,7 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
/* MIPS32 or MIPS64 compliant CPU. */ /* MIPS32 or MIPS64 compliant CPU. */
c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
c->scache.flags = MIPS_CACHE_NOT_PRESENT; c->scache.flags = MIPS_CACHE_NOT_PRESENT;
......
arch/mips/kernel/proc.c
View file @ 03751e79
...@@ -41,27 +41,27 @@ static int show_cpuinfo(struct seq_file *m, void *v) ...@@ -41,27 +41,27 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "processor\t\t: %ld\n", n); seq_printf(m, "processor\t\t: %ld\n", n);
sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
seq_printf(m, fmt, __cpu_name[n], seq_printf(m, fmt, __cpu_name[n],
(version >> 4) & 0x0f, version & 0x0f, (version >> 4) & 0x0f, version & 0x0f,
(fp_vers >> 4) & 0x0f, fp_vers & 0x0f); (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
cpu_data[n].udelay_val / (500000/HZ), cpu_data[n].udelay_val / (500000/HZ),
(cpu_data[n].udelay_val / (5000/HZ)) % 100); (cpu_data[n].udelay_val / (5000/HZ)) % 100);
seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
seq_printf(m, "microsecond timers\t: %s\n", seq_printf(m, "microsecond timers\t: %s\n",
cpu_has_counter ? "yes" : "no"); cpu_has_counter ? "yes" : "no");
seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
seq_printf(m, "extra interrupt vector\t: %s\n", seq_printf(m, "extra interrupt vector\t: %s\n",
cpu_has_divec ? "yes" : "no"); cpu_has_divec ? "yes" : "no");
seq_printf(m, "hardware watchpoint\t: %s", seq_printf(m, "hardware watchpoint\t: %s",
cpu_has_watch ? "yes, " : "no\n"); cpu_has_watch ? "yes, " : "no\n");
if (cpu_has_watch) { if (cpu_has_watch) {
seq_printf(m, "count: %d, address/irw mask: [", seq_printf(m, "count: %d, address/irw mask: [",
cpu_data[n].watch_reg_count); cpu_data[n].watch_reg_count);
for (i = 0; i < cpu_data[n].watch_reg_count; i++) for (i = 0; i < cpu_data[n].watch_reg_count; i++)
seq_printf(m, "%s0x%04x", i ? ", " : "" , seq_printf(m, "%s0x%04x", i ? ", " : "" ,
cpu_data[n].watch_reg_masks[i]); cpu_data[n].watch_reg_masks[i]);
seq_printf(m, "]\n"); seq_printf(m, "]\n");
} }
seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n", seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
...@@ -73,13 +73,13 @@ static int show_cpuinfo(struct seq_file *m, void *v) ...@@ -73,13 +73,13 @@ static int show_cpuinfo(struct seq_file *m, void *v)
cpu_has_mipsmt ? " mt" : "" cpu_has_mipsmt ? " mt" : ""
); );
seq_printf(m, "shadow register sets\t: %d\n", seq_printf(m, "shadow register sets\t: %d\n",
cpu_data[n].srsets); cpu_data[n].srsets);
seq_printf(m, "kscratch registers\t: %d\n", seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask)); hweight8(cpu_data[n].kscratch_mask));
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
cpu_has_vce ? "%u" : "not available"); cpu_has_vce ? "%u" : "not available");
seq_printf(m, fmt, 'D', vced_count); seq_printf(m, fmt, 'D', vced_count);
seq_printf(m, fmt, 'I', vcei_count); seq_printf(m, fmt, 'I', vcei_count);
seq_printf(m, "\n"); seq_printf(m, "\n");
......
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