Commit 0438a105 authored by Zhao Yan's avatar Zhao Yan Committed by Zhi Wang

drm/i915/gvt: do not return error on handling force_to_nonpriv registers

Return error will cause vm hang and enter failsafe mode.
However, we don't want that happen on detecting an wrong force_to_nonpriv
register write.
Therefore, we just omit the wrong write or patch it to default value.

v2: only return 0 on detecting lri write of registers outside whitelist,
but still return error on other error conditions.  (zhenyu wang)
Signed-off-by: default avatarZhao Yan <yan.y.zhao@intel.com>
Reviewed-by: default avatarZhang Yulei <yulei.zhang@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 3d8b9e25
...@@ -828,7 +828,8 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s, ...@@ -828,7 +828,8 @@ static int force_nonpriv_reg_handler(struct parser_exec_state *s,
data != nopid) { data != nopid) {
gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n", gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",
offset, data); offset, data);
return -EPERM; patch_value(s, cmd_ptr(s, index), nopid);
return 0;
} }
return 0; return 0;
} }
......
...@@ -495,7 +495,7 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu, ...@@ -495,7 +495,7 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu,
gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n", gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
vgpu->id, reg_nonpriv, offset); vgpu->id, reg_nonpriv, offset);
return ret; return 0;
} }
static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
......
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