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Commit 05a31b94 authored by Caleb Connolly's avatar Caleb Connolly Committed by Jakub Kicinski
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net: ipa: fix v3.1 resource limit masks 

The resource group limits for IPA v3.1 mistakenly used 6 bit wide mask
values, when the hardware actually uses 8. Out of range values were
silently ignored before, so the IPA worked as expected. However the
new generalised register definitions introduce stricter checking here,
they now cause some splats and result in the value 0 being written
instead. Fix the limit bitmask widths so that the correct values can be
written.

Fixes: 1c418c4a ("net: ipa: define resource group/type IPA register fields")
Signed-off-by: default avatarCaleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: default avatarAlex Elder <elder@linaro.org>
Tested-by: default avatarJami Kettunen <jami.kettunen@somainline.org>
Link: https://lore.kernel.org/r/20221024210336.4014983-2-caleb.connolly@linaro.orgSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent f23a566b
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Showing with 32 additions and 64 deletions
drivers/net/ipa/reg/ipa_reg-v3.1.c
View file @ 05a31b94
...@@ -127,112 +127,80 @@ static const u32 ipa_reg_counter_cfg_fmask[] = { ...@@ -127,112 +127,80 @@ static const u32 ipa_reg_counter_cfg_fmask[] = {
IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = { static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0), [X_MIN_LIM] = GENMASK(7, 0),
/* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(15, 8),
[X_MAX_LIM] = GENMASK(13, 8), [Y_MIN_LIM] = GENMASK(23, 16),
/* Bits 14-15 reserved */ [Y_MAX_LIM] = GENMASK(31, 24),
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
}; };
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
0x00000400, 0x0020); 0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = { static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0), [X_MIN_LIM] = GENMASK(7, 0),
/* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(15, 8),
[X_MAX_LIM] = GENMASK(13, 8), [Y_MIN_LIM] = GENMASK(23, 16),
/* Bits 14-15 reserved */ [Y_MAX_LIM] = GENMASK(31, 24),
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
}; };
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
0x00000404, 0x0020); 0x00000404, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = { static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0), [X_MIN_LIM] = GENMASK(7, 0),
/* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(15, 8),
[X_MAX_LIM] = GENMASK(13, 8), [Y_MIN_LIM] = GENMASK(23, 16),
/* Bits 14-15 reserved */ [Y_MAX_LIM] = GENMASK(31, 24),
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
}; };
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
0x00000408, 0x0020); 0x00000408, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = { static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0), [X_MIN_LIM] = GENMASK(7, 0),
/* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(15, 8),
[X_MAX_LIM] = GENMASK(13, 8), [Y_MIN_LIM] = GENMASK(23, 16),
/* Bits 14-15 reserved */ [Y_MAX_LIM] = GENMASK(31, 24),
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
}; };
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
0x0000040c, 0x0020); 0x0000040c, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0), [X_MIN_LIM] = GENMASK(7, 0),
/* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(15, 8),
[X_MAX_LIM] = GENMASK(13, 8), [Y_MIN_LIM] = GENMASK(23, 16),
/* Bits 14-15 reserved */ [Y_MAX_LIM] = GENMASK(31, 24),
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
}; };
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
0x00000500, 0x0020); 0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0), [X_MIN_LIM] = GENMASK(7, 0),
/* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(15, 8),
[X_MAX_LIM] = GENMASK(13, 8), [Y_MIN_LIM] = GENMASK(23, 16),
/* Bits 14-15 reserved */ [Y_MAX_LIM] = GENMASK(31, 24),
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
}; };
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
0x00000504, 0x0020); 0x00000504, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0), [X_MIN_LIM] = GENMASK(7, 0),
/* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(15, 8),
[X_MAX_LIM] = GENMASK(13, 8), [Y_MIN_LIM] = GENMASK(23, 16),
/* Bits 14-15 reserved */ [Y_MAX_LIM] = GENMASK(31, 24),
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
}; };
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
0x00000508, 0x0020); 0x00000508, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
[X_MIN_LIM] = GENMASK(5, 0), [X_MIN_LIM] = GENMASK(7, 0),
/* Bits 6-7 reserved */ [X_MAX_LIM] = GENMASK(15, 8),
[X_MAX_LIM] = GENMASK(13, 8), [Y_MIN_LIM] = GENMASK(23, 16),
/* Bits 14-15 reserved */ [Y_MAX_LIM] = GENMASK(31, 24),
[Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
}; };
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
......
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