Commit 05ab303b authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'arc-4.13-rc7-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC fixes from Vineet Gupta:

 - PAE40 related updates

 - SLC errata for region ops

 - intc line masking by default

* tag 'arc-4.13-rc7-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  arc: Mask individual IRQ lines during core INTC init
  ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC
  ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addresses
  ARC: dma: implement dma_unmap_page and sg variant
  ARCv2: SLC: Make sure busy bit is set properly for region ops
  ARC: [plat-sim] Include this platform unconditionally
  ARC: [plat-axs10x]: prepare dts files for enabling PAE40 on axs103
  ARC: defconfig: Cleanup from old Kconfig options
parents 0b3baec8 a8ec3ee8
...@@ -96,7 +96,6 @@ menu "ARC Architecture Configuration" ...@@ -96,7 +96,6 @@ menu "ARC Architecture Configuration"
menu "ARC Platform/SoC/Board" menu "ARC Platform/SoC/Board"
source "arch/arc/plat-sim/Kconfig"
source "arch/arc/plat-tb10x/Kconfig" source "arch/arc/plat-tb10x/Kconfig"
source "arch/arc/plat-axs10x/Kconfig" source "arch/arc/plat-axs10x/Kconfig"
#New platform adds here #New platform adds here
......
...@@ -107,7 +107,7 @@ core-y += arch/arc/ ...@@ -107,7 +107,7 @@ core-y += arch/arc/
# w/o this dtb won't embed into kernel binary # w/o this dtb won't embed into kernel binary
core-y += arch/arc/boot/dts/ core-y += arch/arc/boot/dts/
core-$(CONFIG_ARC_PLAT_SIM) += arch/arc/plat-sim/ core-y += arch/arc/plat-sim/
core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/ core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/
core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/ core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/ core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/
......
...@@ -15,15 +15,15 @@ ...@@ -15,15 +15,15 @@
/ { / {
compatible = "snps,arc"; compatible = "snps,arc";
#address-cells = <1>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <2>;
cpu_card { cpu_card {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x00000000 0xf0000000 0x10000000>; ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
core_clk: core_clk { core_clk: core_clk {
#clock-cells = <0>; #clock-cells = <0>;
...@@ -91,23 +91,21 @@ arcpct0: pct { ...@@ -91,23 +91,21 @@ arcpct0: pct {
mb_intc: dw-apb-ictl@0xe0012000 { mb_intc: dw-apb-ictl@0xe0012000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl"; compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >; reg = < 0x0 0xe0012000 0x0 0x200 >;
interrupt-controller; interrupt-controller;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
interrupts = < 7 >; interrupts = < 7 >;
}; };
memory { memory {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x80000000 0x20000000>;
device_type = "memory"; device_type = "memory";
reg = <0x80000000 0x1b000000>; /* (512 - 32) MiB */ /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
}; };
reserved-memory { reserved-memory {
#address-cells = <1>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <2>;
ranges; ranges;
/* /*
* We just move frame buffer area to the very end of * We just move frame buffer area to the very end of
...@@ -118,7 +116,7 @@ reserved-memory { ...@@ -118,7 +116,7 @@ reserved-memory {
*/ */
frame_buffer: frame_buffer@9e000000 { frame_buffer: frame_buffer@9e000000 {
compatible = "shared-dma-pool"; compatible = "shared-dma-pool";
reg = <0x9e000000 0x2000000>; reg = <0x0 0x9e000000 0x0 0x2000000>;
no-map; no-map;
}; };
}; };
......
...@@ -14,15 +14,15 @@ ...@@ -14,15 +14,15 @@
/ { / {
compatible = "snps,arc"; compatible = "snps,arc";
#address-cells = <1>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <2>;
cpu_card { cpu_card {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x00000000 0xf0000000 0x10000000>; ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
core_clk: core_clk { core_clk: core_clk {
#clock-cells = <0>; #clock-cells = <0>;
...@@ -94,30 +94,29 @@ arcpct0: pct { ...@@ -94,30 +94,29 @@ arcpct0: pct {
mb_intc: dw-apb-ictl@0xe0012000 { mb_intc: dw-apb-ictl@0xe0012000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl"; compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >; reg = < 0x0 0xe0012000 0x0 0x200 >;
interrupt-controller; interrupt-controller;
interrupt-parent = <&core_intc>; interrupt-parent = <&core_intc>;
interrupts = < 24 >; interrupts = < 24 >;
}; };
memory { memory {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x80000000 0x40000000>;
device_type = "memory"; device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MiB */ /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
}; };
reserved-memory { reserved-memory {
#address-cells = <1>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <2>;
ranges; ranges;
/* /*
* Move frame buffer out of IOC aperture (0x8z-0xAz). * Move frame buffer out of IOC aperture (0x8z-0xAz).
*/ */
frame_buffer: frame_buffer@be000000 { frame_buffer: frame_buffer@be000000 {
compatible = "shared-dma-pool"; compatible = "shared-dma-pool";
reg = <0xbe000000 0x2000000>; reg = <0x0 0xbe000000 0x0 0x2000000>;
no-map; no-map;
}; };
}; };
......
...@@ -14,15 +14,15 @@ ...@@ -14,15 +14,15 @@
/ { / {
compatible = "snps,arc"; compatible = "snps,arc";
#address-cells = <1>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <2>;
cpu_card { cpu_card {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x00000000 0xf0000000 0x10000000>; ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
core_clk: core_clk { core_clk: core_clk {
#clock-cells = <0>; #clock-cells = <0>;
...@@ -100,30 +100,29 @@ arcpct0: pct { ...@@ -100,30 +100,29 @@ arcpct0: pct {
mb_intc: dw-apb-ictl@0xe0012000 { mb_intc: dw-apb-ictl@0xe0012000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
compatible = "snps,dw-apb-ictl"; compatible = "snps,dw-apb-ictl";
reg = < 0xe0012000 0x200 >; reg = < 0x0 0xe0012000 0x0 0x200 >;
interrupt-controller; interrupt-controller;
interrupt-parent = <&idu_intc>; interrupt-parent = <&idu_intc>;
interrupts = <0>; interrupts = <0>;
}; };
memory { memory {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x80000000 0x40000000>;
device_type = "memory"; device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MiB */ /* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */
reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MiB low mem */
0x1 0xc0000000 0x0 0x40000000>; /* 1 GiB highmem */
}; };
reserved-memory { reserved-memory {
#address-cells = <1>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <2>;
ranges; ranges;
/* /*
* Move frame buffer out of IOC aperture (0x8z-0xAz). * Move frame buffer out of IOC aperture (0x8z-0xAz).
*/ */
frame_buffer: frame_buffer@be000000 { frame_buffer: frame_buffer@be000000 {
compatible = "shared-dma-pool"; compatible = "shared-dma-pool";
reg = <0xbe000000 0x2000000>; reg = <0x0 0xbe000000 0x0 0x2000000>;
no-map; no-map;
}; };
}; };
......
...@@ -13,7 +13,7 @@ axs10x_mb { ...@@ -13,7 +13,7 @@ axs10x_mb {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x00000000 0xe0000000 0x10000000>; ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
interrupt-parent = <&mb_intc>; interrupt-parent = <&mb_intc>;
i2sclk: i2sclk@100a0 { i2sclk: i2sclk@100a0 {
......
...@@ -21,7 +21,6 @@ CONFIG_MODULES=y ...@@ -21,7 +21,6 @@ CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ISA_ARCV2=y CONFIG_ISA_ARCV2=y
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs" CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs"
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
......
...@@ -23,7 +23,6 @@ CONFIG_MODULES=y ...@@ -23,7 +23,6 @@ CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ISA_ARCV2=y CONFIG_ISA_ARCV2=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu" CONFIG_ARC_BUILTIN_DTB_NAME="haps_hs_idu"
......
...@@ -39,7 +39,6 @@ CONFIG_IP_PNP=y ...@@ -39,7 +39,6 @@ CONFIG_IP_PNP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set # CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set # CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set # CONFIG_WIRELESS is not set
......
...@@ -23,7 +23,6 @@ CONFIG_MODULES=y ...@@ -23,7 +23,6 @@ CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_700" CONFIG_ARC_BUILTIN_DTB_NAME="nsim_700"
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set # CONFIG_COMPACTION is not set
......
...@@ -26,7 +26,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y ...@@ -26,7 +26,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ISA_ARCV2=y CONFIG_ISA_ARCV2=y
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs" CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs"
CONFIG_PREEMPT=y CONFIG_PREEMPT=y
......
...@@ -24,7 +24,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y ...@@ -24,7 +24,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ISA_ARCV2=y CONFIG_ISA_ARCV2=y
CONFIG_SMP=y CONFIG_SMP=y
CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs_idu" CONFIG_ARC_BUILTIN_DTB_NAME="nsim_hs_idu"
......
...@@ -23,7 +23,6 @@ CONFIG_MODULES=y ...@@ -23,7 +23,6 @@ CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci" CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci"
# CONFIG_COMPACTION is not set # CONFIG_COMPACTION is not set
CONFIG_NET=y CONFIG_NET=y
......
...@@ -23,7 +23,6 @@ CONFIG_MODULES=y ...@@ -23,7 +23,6 @@ CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ISA_ARCV2=y CONFIG_ISA_ARCV2=y
CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs" CONFIG_ARC_BUILTIN_DTB_NAME="nsimosci_hs"
# CONFIG_COMPACTION is not set # CONFIG_COMPACTION is not set
......
...@@ -18,7 +18,6 @@ CONFIG_MODULES=y ...@@ -18,7 +18,6 @@ CONFIG_MODULES=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set # CONFIG_IOSCHED_CFQ is not set
CONFIG_ARC_PLAT_SIM=y
CONFIG_ISA_ARCV2=y CONFIG_ISA_ARCV2=y
CONFIG_SMP=y CONFIG_SMP=y
# CONFIG_ARC_TIMERS_64BIT is not set # CONFIG_ARC_TIMERS_64BIT is not set
......
...@@ -38,7 +38,6 @@ CONFIG_IP_MULTICAST=y ...@@ -38,7 +38,6 @@ CONFIG_IP_MULTICAST=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set # CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set # CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set # CONFIG_WIRELESS is not set
......
...@@ -96,7 +96,9 @@ extern unsigned long perip_base, perip_end; ...@@ -96,7 +96,9 @@ extern unsigned long perip_base, perip_end;
#define ARC_REG_SLC_FLUSH 0x904 #define ARC_REG_SLC_FLUSH 0x904
#define ARC_REG_SLC_INVALIDATE 0x905 #define ARC_REG_SLC_INVALIDATE 0x905
#define ARC_REG_SLC_RGN_START 0x914 #define ARC_REG_SLC_RGN_START 0x914
#define ARC_REG_SLC_RGN_START1 0x915
#define ARC_REG_SLC_RGN_END 0x916 #define ARC_REG_SLC_RGN_END 0x916
#define ARC_REG_SLC_RGN_END1 0x917
/* Bit val in SLC_CONTROL */ /* Bit val in SLC_CONTROL */
#define SLC_CTRL_DIS 0x001 #define SLC_CTRL_DIS 0x001
......
...@@ -94,6 +94,8 @@ static inline int is_pae40_enabled(void) ...@@ -94,6 +94,8 @@ static inline int is_pae40_enabled(void)
return IS_ENABLED(CONFIG_ARC_HAS_PAE40); return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
} }
extern int pae40_exist_but_not_enab(void);
#endif /* !__ASSEMBLY__ */ #endif /* !__ASSEMBLY__ */
#endif #endif
...@@ -75,10 +75,13 @@ void arc_init_IRQ(void) ...@@ -75,10 +75,13 @@ void arc_init_IRQ(void)
* Set a default priority for all available interrupts to prevent * Set a default priority for all available interrupts to prevent
* switching of register banks if Fast IRQ and multiple register banks * switching of register banks if Fast IRQ and multiple register banks
* are supported by CPU. * are supported by CPU.
* Also disable all IRQ lines so faulty external hardware won't
* trigger interrupt that kernel is not ready to handle.
*/ */
for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) {
write_aux_reg(AUX_IRQ_SELECT, i); write_aux_reg(AUX_IRQ_SELECT, i);
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
write_aux_reg(AUX_IRQ_ENABLE, 0);
} }
/* setup status32, don't enable intr yet as kernel doesn't want */ /* setup status32, don't enable intr yet as kernel doesn't want */
......
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
*/ */
void arc_init_IRQ(void) void arc_init_IRQ(void)
{ {
int level_mask = 0; int level_mask = 0, i;
/* Is timer high priority Interrupt (Level2 in ARCompact jargon) */ /* Is timer high priority Interrupt (Level2 in ARCompact jargon) */
level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ; level_mask |= IS_ENABLED(CONFIG_ARC_COMPACT_IRQ_LEVELS) << TIMER0_IRQ;
...@@ -40,6 +40,18 @@ void arc_init_IRQ(void) ...@@ -40,6 +40,18 @@ void arc_init_IRQ(void)
if (level_mask) if (level_mask)
pr_info("Level-2 interrupts bitset %x\n", level_mask); pr_info("Level-2 interrupts bitset %x\n", level_mask);
/*
* Disable all IRQ lines so faulty external hardware won't
* trigger interrupt that kernel is not ready to handle.
*/
for (i = TIMER0_IRQ; i < NR_CPU_IRQS; i++) {
unsigned int ienb;
ienb = read_aux_reg(AUX_IENABLE);
ienb &= ~(1 << i);
write_aux_reg(AUX_IENABLE, ienb);
}
} }
/* /*
......
...@@ -665,6 +665,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) ...@@ -665,6 +665,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
static DEFINE_SPINLOCK(lock); static DEFINE_SPINLOCK(lock);
unsigned long flags; unsigned long flags;
unsigned int ctrl; unsigned int ctrl;
phys_addr_t end;
spin_lock_irqsave(&lock, flags); spin_lock_irqsave(&lock, flags);
...@@ -694,8 +695,19 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) ...@@ -694,8 +695,19 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
* END needs to be setup before START (latter triggers the operation) * END needs to be setup before START (latter triggers the operation)
* END can't be same as START, so add (l2_line_sz - 1) to sz * END can't be same as START, so add (l2_line_sz - 1) to sz
*/ */
write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1)); end = paddr + sz + l2_line_sz - 1;
write_aux_reg(ARC_REG_SLC_RGN_START, paddr); if (is_pae40_enabled())
write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
if (is_pae40_enabled())
write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
read_aux_reg(ARC_REG_SLC_CTRL);
while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
...@@ -1111,6 +1123,13 @@ noinline void __init arc_ioc_setup(void) ...@@ -1111,6 +1123,13 @@ noinline void __init arc_ioc_setup(void)
__dc_enable(); __dc_enable();
} }
/*
* Cache related boot time checks/setups only needed on master CPU:
* - Geometry checks (kernel build and hardware agree: e.g. L1_CACHE_BYTES)
* Assume SMP only, so all cores will have same cache config. A check on
* one core suffices for all
* - IOC setup / dma callbacks only need to be done once
*/
void __init arc_cache_init_master(void) void __init arc_cache_init_master(void)
{ {
unsigned int __maybe_unused cpu = smp_processor_id(); unsigned int __maybe_unused cpu = smp_processor_id();
...@@ -1190,12 +1209,27 @@ void __ref arc_cache_init(void) ...@@ -1190,12 +1209,27 @@ void __ref arc_cache_init(void)
printk(arc_cache_mumbojumbo(0, str, sizeof(str))); printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
/*
* Only master CPU needs to execute rest of function:
* - Assume SMP so all cores will have same cache config so
* any geomtry checks will be same for all
* - IOC setup / dma callbacks only need to be setup once
*/
if (!cpu) if (!cpu)
arc_cache_init_master(); arc_cache_init_master();
/*
* In PAE regime, TLB and cache maintenance ops take wider addresses
* And even if PAE is not enabled in kernel, the upper 32-bits still need
* to be zeroed to keep the ops sane.
* As an optimization for more common !PAE enabled case, zero them out
* once at init, rather than checking/setting to 0 for every runtime op
*/
if (is_isa_arcv2() && pae40_exist_but_not_enab()) {
if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE))
write_aux_reg(ARC_REG_IC_PTAG_HI, 0);
if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE))
write_aux_reg(ARC_REG_DC_PTAG_HI, 0);
if (l2_line_sz) {
write_aux_reg(ARC_REG_SLC_RGN_END1, 0);
write_aux_reg(ARC_REG_SLC_RGN_START1, 0);
}
}
} }
...@@ -153,6 +153,19 @@ static void _dma_cache_sync(phys_addr_t paddr, size_t size, ...@@ -153,6 +153,19 @@ static void _dma_cache_sync(phys_addr_t paddr, size_t size,
} }
} }
/*
* arc_dma_map_page - map a portion of a page for streaming DMA
*
* Ensure that any data held in the cache is appropriately discarded
* or written back.
*
* The device owns this memory once this call has completed. The CPU
* can regain ownership by calling dma_unmap_page().
*
* Note: while it takes struct page as arg, caller can "abuse" it to pass
* a region larger than PAGE_SIZE, provided it is physically contiguous
* and this still works correctly
*/
static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page, static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size, enum dma_data_direction dir, unsigned long offset, size_t size, enum dma_data_direction dir,
unsigned long attrs) unsigned long attrs)
...@@ -165,6 +178,24 @@ static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page, ...@@ -165,6 +178,24 @@ static dma_addr_t arc_dma_map_page(struct device *dev, struct page *page,
return plat_phys_to_dma(dev, paddr); return plat_phys_to_dma(dev, paddr);
} }
/*
* arc_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
*
* After this call, reads by the CPU to the buffer are guaranteed to see
* whatever the device wrote there.
*
* Note: historically this routine was not implemented for ARC
*/
static void arc_dma_unmap_page(struct device *dev, dma_addr_t handle,
size_t size, enum dma_data_direction dir,
unsigned long attrs)
{
phys_addr_t paddr = plat_dma_to_phys(dev, handle);
if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC))
_dma_cache_sync(paddr, size, dir);
}
static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg, static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir, unsigned long attrs) int nents, enum dma_data_direction dir, unsigned long attrs)
{ {
...@@ -178,6 +209,18 @@ static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg, ...@@ -178,6 +209,18 @@ static int arc_dma_map_sg(struct device *dev, struct scatterlist *sg,
return nents; return nents;
} }
static void arc_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir,
unsigned long attrs)
{
struct scatterlist *s;
int i;
for_each_sg(sg, s, nents, i)
arc_dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir,
attrs);
}
static void arc_dma_sync_single_for_cpu(struct device *dev, static void arc_dma_sync_single_for_cpu(struct device *dev,
dma_addr_t dma_handle, size_t size, enum dma_data_direction dir) dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
{ {
...@@ -223,7 +266,9 @@ const struct dma_map_ops arc_dma_ops = { ...@@ -223,7 +266,9 @@ const struct dma_map_ops arc_dma_ops = {
.free = arc_dma_free, .free = arc_dma_free,
.mmap = arc_dma_mmap, .mmap = arc_dma_mmap,
.map_page = arc_dma_map_page, .map_page = arc_dma_map_page,
.unmap_page = arc_dma_unmap_page,
.map_sg = arc_dma_map_sg, .map_sg = arc_dma_map_sg,
.unmap_sg = arc_dma_unmap_sg,
.sync_single_for_device = arc_dma_sync_single_for_device, .sync_single_for_device = arc_dma_sync_single_for_device,
.sync_single_for_cpu = arc_dma_sync_single_for_cpu, .sync_single_for_cpu = arc_dma_sync_single_for_cpu,
.sync_sg_for_cpu = arc_dma_sync_sg_for_cpu, .sync_sg_for_cpu = arc_dma_sync_sg_for_cpu,
......
...@@ -104,6 +104,8 @@ ...@@ -104,6 +104,8 @@
/* A copy of the ASID from the PID reg is kept in asid_cache */ /* A copy of the ASID from the PID reg is kept in asid_cache */
DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE; DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;
static int __read_mostly pae_exists;
/* /*
* Utility Routine to erase a J-TLB entry * Utility Routine to erase a J-TLB entry
* Caller needs to setup Index Reg (manually or via getIndex) * Caller needs to setup Index Reg (manually or via getIndex)
...@@ -784,7 +786,7 @@ void read_decode_mmu_bcr(void) ...@@ -784,7 +786,7 @@ void read_decode_mmu_bcr(void)
mmu->u_dtlb = mmu4->u_dtlb * 4; mmu->u_dtlb = mmu4->u_dtlb * 4;
mmu->u_itlb = mmu4->u_itlb * 4; mmu->u_itlb = mmu4->u_itlb * 4;
mmu->sasid = mmu4->sasid; mmu->sasid = mmu4->sasid;
mmu->pae = mmu4->pae; pae_exists = mmu->pae = mmu4->pae;
} }
} }
...@@ -809,6 +811,11 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len) ...@@ -809,6 +811,11 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
return buf; return buf;
} }
int pae40_exist_but_not_enab(void)
{
return pae_exists && !is_pae40_enabled();
}
void arc_mmu_init(void) void arc_mmu_init(void)
{ {
char str[256]; char str[256];
...@@ -859,6 +866,9 @@ void arc_mmu_init(void) ...@@ -859,6 +866,9 @@ void arc_mmu_init(void)
/* swapper_pg_dir is the pgd for the kernel, used by vmalloc */ /* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir); write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
#endif #endif
if (pae40_exist_but_not_enab())
write_aux_reg(ARC_REG_TLBPD1HI, 0);
} }
/* /*
......
#
# Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License version 2 as
# published by the Free Software Foundation.
#
menuconfig ARC_PLAT_SIM
bool "ARC nSIM based simulation virtual platforms"
help
Support for nSIM based ARC simulation platforms
This includes the standalone nSIM (uart only) vs. System C OSCI VP
...@@ -20,11 +20,14 @@ ...@@ -20,11 +20,14 @@
*/ */
static const char *simulation_compat[] __initconst = { static const char *simulation_compat[] __initconst = {
#ifdef CONFIG_ISA_ARCOMPACT
"snps,nsim", "snps,nsim",
"snps,nsim_hs",
"snps,nsimosci", "snps,nsimosci",
#else
"snps,nsim_hs",
"snps,nsimosci_hs", "snps,nsimosci_hs",
"snps,zebu_hs", "snps,zebu_hs",
#endif
NULL, NULL,
}; };
......
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