drm/amdgpu/display: Add dml support for DCN

Display mode lib handles clock, watermark, and bandwidth
calculations for DCN.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dml/Makefile

+#
+# Makefile for the 'utils' sub-component of DAL.
+# It provides the general basic services required by other DAL
+# subcomponents.
+
+CFLAGS_display_mode_lib.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_pipe_clocks.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_rq_dlg_calc.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_rq_dlg_helpers.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_watermark.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_soc_bounding_box.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_dml_common_defs.o := -mhard-float -msse -mpreferred-stack-boundary=4
+CFLAGS_display_mode_support.o := -mhard-float -msse -mpreferred-stack-boundary=4
+
+
+DML = display_mode_lib.o display_pipe_clocks.o display_rq_dlg_calc.o \
+	  display_rq_dlg_helpers.o display_watermark.o \
+	  soc_bounding_box.o dml_common_defs.o display_mode_support.o
+
+AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_DML)

drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_MODE_ENUMS_H__
+#define __DISPLAY_MODE_ENUMS_H__
+enum output_encoder_class {
+	dm_dp = 0,
+	dm_hdmi = 1,
+	dm_wb = 2
+};
+enum output_format_class {
+	dm_444 = 0,
+	dm_420 = 1
+};
+enum source_format_class {
+	dm_444_16 = 0,
+	dm_444_32 = 1,
+	dm_444_64 = 2,
+	dm_420_8 = 3,
+	dm_420_10 = 4,
+	dm_422_8 = 5,
+	dm_422_10 = 6
+};
+enum output_bpc_class {
+	dm_out_6 = 0,
+	dm_out_8 = 1,
+	dm_out_10 = 2,
+	dm_out_12 = 3,
+	dm_out_16 = 4
+};
+enum scan_direction_class {
+	dm_horz = 0,
+	dm_vert = 1
+};
+enum dm_swizzle_mode {
+	dm_sw_linear = 0,
+	dm_sw_256b_s = 1,
+	dm_sw_256b_d = 2,
+	dm_sw_SPARE_0 = 3,
+	dm_sw_SPARE_1 = 4,
+	dm_sw_4kb_s = 5,
+	dm_sw_4kb_d = 6,
+	dm_sw_SPARE_2 = 7,
+	dm_sw_SPARE_3 = 8,
+	dm_sw_64kb_s = 9,
+	dm_sw_64kb_d = 10,
+	dm_sw_SPARE_4 = 11,
+	dm_sw_SPARE_5 = 12,
+	dm_sw_var_s = 13,
+	dm_sw_var_d = 14,
+	dm_sw_SPARE_6 = 15,
+	dm_sw_SPARE_7 = 16,
+	dm_sw_64kb_s_t = 17,
+	dm_sw_64kb_d_t = 18,
+	dm_sw_SPARE_10 = 19,
+	dm_sw_SPARE_11 = 20,
+	dm_sw_4kb_s_x = 21,
+	dm_sw_4kb_d_x = 22,
+	dm_sw_SPARE_12 = 23,
+	dm_sw_SPARE_13 = 24,
+	dm_sw_64kb_s_x = 25,
+	dm_sw_64kb_d_x = 26,
+	dm_sw_SPARE_14 = 27,
+	dm_sw_SPARE_15 = 28,
+	dm_sw_var_s_x = 29,
+	dm_sw_var_d_x = 30
+};
+enum lb_depth {
+	dm_lb_10 = 30,
+	dm_lb_8 = 24,
+	dm_lb_6 = 18,
+	dm_lb_12 = 36
+};
+enum voltage_state {
+	dm_vmin = 0,
+	dm_vmid = 1,
+	dm_vnom = 2,
+	dm_vmax = 3,
+	dm_vmax_exceeded = 4
+};
+enum source_macro_tile_size {
+	dm_4k_tile = 0,
+	dm_64k_tile = 1,
+	dm_256k_tile = 2
+};
+enum cursor_bpp {
+	dm_cur_2bit = 0,
+	dm_cur_32bit = 1
+};
+#endif

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "display_mode_lib.h"
+
+static void set_soc_bounding_box(struct _vcs_dpi_soc_bounding_box_st *soc, enum dml_project project)
+{
+	if (project == DML_PROJECT_RAVEN1) {
+		soc->sr_exit_time_us = 9.0;
+		soc->sr_enter_plus_exit_time_us = 11.0;
+		soc->urgent_latency_us = 4.0;
+		soc->writeback_latency_us = 12.0;
+		soc->ideal_dram_bw_after_urgent_percent = 80.0;
+		soc->max_request_size_bytes = 256;
+
+		soc->vmin.dcfclk_mhz = 300.0;
+		soc->vmin.dispclk_mhz = 608.0;
+		soc->vmin.dppclk_mhz = 435.0;
+		soc->vmin.dram_bw_per_chan_gbps = 12.8;
+		soc->vmin.phyclk_mhz = 540.0;
+		soc->vmin.socclk_mhz = 208.0;
+
+		soc->vmid.dcfclk_mhz = 600.0;
+		soc->vmid.dispclk_mhz = 661.0;
+		soc->vmid.dppclk_mhz = 661.0;
+		soc->vmid.dram_bw_per_chan_gbps = 12.8;
+		soc->vmid.phyclk_mhz = 540.0;
+		soc->vmid.socclk_mhz = 208.0;
+
+		soc->vnom.dcfclk_mhz = 600.0;
+		soc->vnom.dispclk_mhz = 661.0;
+		soc->vnom.dppclk_mhz = 661.0;
+		soc->vnom.dram_bw_per_chan_gbps = 38.4;
+		soc->vnom.phyclk_mhz = 810;
+		soc->vnom.socclk_mhz = 208.0;
+
+		soc->vmax.dcfclk_mhz = 600.0;
+		soc->vmax.dispclk_mhz = 1086.0;
+		soc->vmax.dppclk_mhz = 661.0;
+		soc->vmax.dram_bw_per_chan_gbps = 38.4;
+		soc->vmax.phyclk_mhz = 810.0;
+		soc->vmax.socclk_mhz = 208.0;
+
+		soc->downspread_percent = 0.5;
+		soc->dram_page_open_time_ns = 50.0;
+		soc->dram_rw_turnaround_time_ns = 17.5;
+		soc->dram_return_buffer_per_channel_bytes = 8192;
+		soc->round_trip_ping_latency_dcfclk_cycles = 128;
+		soc->urgent_out_of_order_return_per_channel_bytes = 256;
+		soc->channel_interleave_bytes = 256;
+		soc->num_banks = 8;
+		soc->num_chans = 2;
+		soc->vmm_page_size_bytes = 4096;
+		soc->dram_clock_change_latency_us = 17.0;
+		soc->writeback_dram_clock_change_latency_us = 23.0;
+		soc->return_bus_width_bytes = 64;
+	} else {
+		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
+	}
+}
+
+static void set_ip_params(struct _vcs_dpi_ip_params_st *ip, enum dml_project project)
+{
+	if (project == DML_PROJECT_RAVEN1) {
+		ip->rob_buffer_size_kbytes = 64;
+		ip->det_buffer_size_kbytes = 164;
+		ip->dpte_buffer_size_in_pte_reqs = 42;
+		ip->dpp_output_buffer_pixels = 2560;
+		ip->opp_output_buffer_lines = 1;
+		ip->pixel_chunk_size_kbytes = 8;
+		ip->pte_enable = 1;
+		ip->pte_chunk_size_kbytes = 2;
+		ip->meta_chunk_size_kbytes = 2;
+		ip->writeback_chunk_size_kbytes = 2;
+		ip->line_buffer_size_bits = 589824;
+		ip->max_line_buffer_lines = 12;
+		ip->IsLineBufferBppFixed = 0;
+		ip->LineBufferFixedBpp = -1;
+		ip->writeback_luma_buffer_size_kbytes = 12;
+		ip->writeback_chroma_buffer_size_kbytes = 8;
+		ip->max_num_dpp = 4;
+		ip->max_num_wb = 2;
+		ip->max_dchub_pscl_bw_pix_per_clk = 4;
+		ip->max_pscl_lb_bw_pix_per_clk = 2;
+		ip->max_lb_vscl_bw_pix_per_clk = 4;
+		ip->max_vscl_hscl_bw_pix_per_clk = 4;
+		ip->max_hscl_ratio = 4;
+		ip->max_vscl_ratio = 4;
+		ip->hscl_mults = 4;
+		ip->vscl_mults = 4;
+		ip->max_hscl_taps = 8;
+		ip->max_vscl_taps = 8;
+		ip->dispclk_ramp_margin_percent = 1;
+		ip->underscan_factor = 1.10;
+		ip->min_vblank_lines = 14;
+		ip->dppclk_delay_subtotal = 90;
+		ip->dispclk_delay_subtotal = 42;
+		ip->dcfclk_cstate_latency = 10;
+		ip->max_inter_dcn_tile_repeaters = 8;
+		ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0;
+		ip->bug_forcing_LC_req_same_size_fixed = 0;
+	} else {
+		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
+	}
+}
+
+static void set_mode_evaluation(struct _vcs_dpi_mode_evaluation_st *me, enum dml_project project)
+{
+	if (project == DML_PROJECT_RAVEN1) {
+		me->voltage_override = dm_vmin;
+	} else {
+		BREAK_TO_DEBUGGER(); /* Invalid Project Specified */
+	}
+}
+
+void dml_init_instance(struct display_mode_lib *lib, enum dml_project project)
+{
+	if (lib->project != project) {
+		set_soc_bounding_box(&lib->soc, project);
+		set_ip_params(&lib->ip, project);
+		set_mode_evaluation(&lib->me, project);
+		lib->project = project;
+	}
+}
+

drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_MODE_LIB_H__
+#define __DISPLAY_MODE_LIB_H__
+
+#include "dml_common_defs.h"
+#include "soc_bounding_box.h"
+#include "display_watermark.h"
+#include "display_pipe_clocks.h"
+#include "display_rq_dlg_calc.h"
+#include "display_mode_support.h"
+
+enum dml_project {
+	DML_PROJECT_UNDEFINED,
+	DML_PROJECT_RAVEN1
+};
+
+struct display_mode_lib {
+	struct _vcs_dpi_ip_params_st ip;
+	struct _vcs_dpi_soc_bounding_box_st soc;
+	struct _vcs_dpi_mode_evaluation_st me;
+	enum dml_project project;
+	struct dml_ms_internal_vars vars;
+	struct _vcs_dpi_wm_calc_pipe_params_st wm_param[DC__NUM_PIPES__MAX];
+	struct dal_logger *logger;
+};
+
+void dml_init_instance(struct display_mode_lib *lib, enum dml_project project);
+
+#endif

drivers/gpu/drm/amd/display/dc/dml/display_mode_support.h

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_MODE_SUPPORT_H__
+#define __DISPLAY_MODE_SUPPORT_H__
+
+#include "dml_common_defs.h"
+
+struct display_mode_lib;
+
+#define NumberOfStates 4
+#define NumberOfStatesPlusTwo (NumberOfStates+2)
+
+struct dml_ms_internal_vars {
+	double ScaleRatioSupport;
+	double SourceFormatPixelAndScanSupport;
+	double TotalReadBandwidthConsumedGBytePerSecond;
+	double TotalWriteBandwidthConsumedGBytePerSecond;
+	double TotalBandwidthConsumedGBytePerSecond;
+	double DCCEnabledInAnyPlane;
+	double ReturnBWToDCNPerState;
+	double CriticalPoint;
+	double WritebackLatencySupport;
+	double RequiredOutputBW;
+	double TotalNumberOfActiveWriteback;
+	double TotalAvailableWritebackSupport;
+	double MaximumSwathWidth;
+	double NumberOfDPPRequiredForDETSize;
+	double NumberOfDPPRequiredForLBSize;
+	double MinDispclkUsingSingleDPP;
+	double MinDispclkUsingDualDPP;
+	double ViewportSizeSupport;
+	double SwathWidthGranularityY;
+	double RoundedUpMaxSwathSizeBytesY;
+	double SwathWidthGranularityC;
+	double RoundedUpMaxSwathSizeBytesC;
+	double LinesInDETLuma;
+	double LinesInDETChroma;
+	double EffectiveLBLatencyHidingSourceLinesLuma;
+	double EffectiveLBLatencyHidingSourceLinesChroma;
+	double EffectiveDETLBLinesLuma;
+	double EffectiveDETLBLinesChroma;
+	double ProjectedDCFCLKDeepSleep;
+	double MetaReqHeightY;
+	double MetaReqWidthY;
+	double MetaSurfaceWidthY;
+	double MetaSurfaceHeightY;
+	double MetaPteBytesPerFrameY;
+	double MetaRowBytesY;
+	double MacroTileBlockSizeBytesY;
+	double MacroTileBlockHeightY;
+	double DataPTEReqHeightY;
+	double DataPTEReqWidthY;
+	double DPTEBytesPerRowY;
+	double MetaReqHeightC;
+	double MetaReqWidthC;
+	double MetaSurfaceWidthC;
+	double MetaSurfaceHeightC;
+	double MetaPteBytesPerFrameC;
+	double MetaRowBytesC;
+	double MacroTileBlockSizeBytesC;
+	double MacroTileBlockHeightC;
+	double MacroTileBlockWidthC;
+	double DataPTEReqHeightC;
+	double DataPTEReqWidthC;
+	double DPTEBytesPerRowC;
+	double VInitY;
+	double MaxPartialSwY;
+	double VInitC;
+	double MaxPartialSwC;
+	double dst_x_after_scaler;
+	double dst_y_after_scaler;
+	double TimeCalc;
+	double VUpdateOffset;
+	double TotalRepeaterDelay;
+	double VUpdateWidth;
+	double VReadyOffset;
+	double TimeSetup;
+	double ExtraLatency;
+	double MaximumVStartup;
+	double BWAvailableForImmediateFlip;
+	double TotalImmediateFlipBytes;
+	double TimeForMetaPTEWithImmediateFlip;
+	double TimeForMetaPTEWithoutImmediateFlip;
+	double TimeForMetaAndDPTERowWithImmediateFlip;
+	double TimeForMetaAndDPTERowWithoutImmediateFlip;
+	double LineTimesToRequestPrefetchPixelDataWithImmediateFlip;
+	double LineTimesToRequestPrefetchPixelDataWithoutImmediateFlip;
+	double MaximumReadBandwidthWithPrefetchWithImmediateFlip;
+	double MaximumReadBandwidthWithPrefetchWithoutImmediateFlip;
+	double VoltageOverrideLevel;
+	double VoltageLevelWithImmediateFlip;
+	double VoltageLevelWithoutImmediateFlip;
+	double ImmediateFlipSupported;
+	double VoltageLevel;
+	double DCFCLK;
+	double FabricAndDRAMBandwidth;
+	double SwathWidthYSingleDPP[DC__NUM_PIPES__MAX];
+	double BytePerPixelInDETY[DC__NUM_PIPES__MAX];
+	double BytePerPixelInDETC[DC__NUM_PIPES__MAX];
+	double ReadBandwidth[DC__NUM_PIPES__MAX];
+	double WriteBandwidth[DC__NUM_PIPES__MAX];
+	double DCFCLKPerState[NumberOfStatesPlusTwo];
+	double FabricAndDRAMBandwidthPerState[NumberOfStatesPlusTwo];
+	double ReturnBWPerState[NumberOfStatesPlusTwo];
+	double BandwidthSupport[NumberOfStatesPlusTwo];
+	double UrgentRoundTripAndOutOfOrderLatencyPerState[NumberOfStatesPlusTwo];
+	double ROBSupport[NumberOfStatesPlusTwo];
+	double RequiredPHYCLK[DC__NUM_PIPES__MAX];
+	double DIOSupport[NumberOfStatesPlusTwo];
+	double PHYCLKPerState[NumberOfStatesPlusTwo];
+	double PSCL_FACTOR[DC__NUM_PIPES__MAX];
+	double PSCL_FACTOR_CHROMA[DC__NUM_PIPES__MAX];
+	double MinDPPCLKUsingSingleDPP[DC__NUM_PIPES__MAX];
+	double Read256BlockHeightY[DC__NUM_PIPES__MAX];
+	double Read256BlockWidthY[DC__NUM_PIPES__MAX];
+	double Read256BlockHeightC[DC__NUM_PIPES__MAX];
+	double Read256BlockWidthC[DC__NUM_PIPES__MAX];
+	double MaxSwathHeightY[DC__NUM_PIPES__MAX];
+	double MaxSwathHeightC[DC__NUM_PIPES__MAX];
+	double MinSwathHeightY[DC__NUM_PIPES__MAX];
+	double MinSwathHeightC[DC__NUM_PIPES__MAX];
+	double NumberOfDPPRequiredForDETAndLBSize[DC__NUM_PIPES__MAX];
+	double TotalNumberOfActiveDPP[NumberOfStatesPlusTwo * 2];
+	double RequiredDISPCLK[NumberOfStatesPlusTwo * 2];
+	double DISPCLK_DPPCLK_Support[NumberOfStatesPlusTwo * 2];
+	double MaxDispclk[NumberOfStatesPlusTwo];
+	double MaxDppclk[NumberOfStatesPlusTwo];
+	double NoOfDPP[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double TotalAvailablePipesSupport[NumberOfStatesPlusTwo * 2];
+	double SwathWidthYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double SwathHeightYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double SwathHeightCPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double DETBufferSizeYPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double UrgentLatencySupportUsPerState[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double UrgentLatencySupport[NumberOfStatesPlusTwo * 2];
+	double TotalNumberOfDCCActiveDPP[NumberOfStatesPlusTwo * 2];
+	double DPTEBytesPerRow[DC__NUM_PIPES__MAX];
+	double MetaPTEBytesPerFrame[DC__NUM_PIPES__MAX];
+	double MetaRowBytes[DC__NUM_PIPES__MAX];
+	double PrefillY[DC__NUM_PIPES__MAX];
+	double MaxNumSwY[DC__NUM_PIPES__MAX];
+	double PrefetchLinesY[DC__NUM_PIPES__MAX];
+	double PrefillC[DC__NUM_PIPES__MAX];
+	double MaxNumSwC[DC__NUM_PIPES__MAX];
+	double PrefetchLinesC[DC__NUM_PIPES__MAX];
+	double LineTimesForPrefetch[DC__NUM_PIPES__MAX];
+	double PrefetchBW[DC__NUM_PIPES__MAX];
+	double LinesForMetaPTEWithImmediateFlip[DC__NUM_PIPES__MAX];
+	double LinesForMetaPTEWithoutImmediateFlip[DC__NUM_PIPES__MAX];
+	double LinesForMetaAndDPTERowWithImmediateFlip[DC__NUM_PIPES__MAX];
+	double LinesForMetaAndDPTERowWithoutImmediateFlip[DC__NUM_PIPES__MAX];
+	double VRatioPreYWithImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double VRatioPreCWithImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double RequiredPrefetchPixelDataBWWithImmediateFlip[NumberOfStatesPlusTwo * 2
+			* DC__NUM_PIPES__MAX];
+	double VRatioPreYWithoutImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double VRatioPreCWithoutImmediateFlip[NumberOfStatesPlusTwo * 2 * DC__NUM_PIPES__MAX];
+	double RequiredPrefetchPixelDataBWWithoutImmediateFlip[NumberOfStatesPlusTwo * 2
+			* DC__NUM_PIPES__MAX];
+	double PrefetchSupportedWithImmediateFlip[NumberOfStatesPlusTwo * 2];
+	double PrefetchSupportedWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
+	double VRatioInPrefetchSupportedWithImmediateFlip[NumberOfStatesPlusTwo * 2];
+	double VRatioInPrefetchSupportedWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
+	double ModeSupportWithImmediateFlip[NumberOfStatesPlusTwo * 2];
+	double ModeSupportWithoutImmediateFlip[NumberOfStatesPlusTwo * 2];
+	double RequiredDISPCLKPerRatio[2];
+	double DPPPerPlanePerRatio[2 * DC__NUM_PIPES__MAX];
+	double DISPCLK_DPPCLK_SupportPerRatio[2];
+	struct _vcs_dpi_wm_calc_pipe_params_st planes[DC__NUM_PIPES__MAX];
+};
+
+int dml_ms_check(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+		int num_pipes);
+
+#endif

drivers/gpu/drm/amd/display/dc/dml/display_pipe_clocks.h

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_PIPE_CLOCKS_H__
+#define __DISPLAY_PIPE_CLOCKS_H__
+
+#include "dml_common_defs.h"
+
+struct display_mode_lib;
+
+struct _vcs_dpi_display_pipe_clock_st dml_clks_get_pipe_clocks(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+		unsigned int num_pipes);
+
+bool dml_clks_pipe_clock_requirement_fit_power_constraint(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+		unsigned int num_dpp_in_grp);
+#endif

drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.h

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_RQ_DLG_CALC_H__
+#define __DISPLAY_RQ_DLG_CALC_H__
+
+#include "dml_common_defs.h"
+#include "display_rq_dlg_helpers.h"
+
+struct display_mode_lib;
+
+void extract_rq_regs(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_rq_regs_st *rq_regs,
+		const struct _vcs_dpi_display_rq_params_st rq_param);
+/* Function: dml_rq_dlg_get_rq_params
+ *  Calculate requestor related parameters that register definition agnostic
+ *  (i.e. this layer does try to separate real values from register defintion)
+ * Input:
+ *  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
+ * Output:
+ *  rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.)
+ */
+void dml_rq_dlg_get_rq_params(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_rq_params_st *rq_param,
+		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
+
+/* Function: dml_rq_dlg_get_rq_reg
+ *  Main entry point for test to get the register values out of this DML class.
+ *  This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
+ *  and then populate the rq_regs struct
+ * Input:
+ *  pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.)
+ * Output:
+ *  rq_regs - struct that holds all the RQ registers field value.
+ *            See also: <display_rq_regs_st>
+ */
+void dml_rq_dlg_get_rq_reg(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_rq_regs_st *rq_regs,
+		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);
+
+/* Function: dml_rq_dlg_get_dlg_params
+ *  Calculate deadline related parameters
+ */
+void dml_rq_dlg_get_dlg_params(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+		struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
+		const struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
+		const struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
+		const struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
+		const bool cstate_en,
+		const bool pstate_en,
+		const bool vm_en,
+		const bool iflip_en);
+
+/* Function: dml_rq_dlg_get_dlg_param_prefetch
+ *   For flip_bw programming guide change, now dml needs to calculate the flip_bytes and prefetch_bw
+ *   for ALL pipes and use this info to calculate the prefetch programming.
+ * Output: prefetch_param.prefetch_bw and flip_bytes
+ */
+void dml_rq_dlg_get_dlg_params_prefetch(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_dlg_prefetch_param_st *prefetch_param,
+		struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param,
+		struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param,
+		struct _vcs_dpi_display_e2e_pipe_params_st e2e_pipe_param,
+		const bool cstate_en,
+		const bool pstate_en,
+		const bool vm_en);
+
+/* Function: dml_rq_dlg_get_dlg_reg
+ *   Calculate and return DLG and TTU register struct given the system setting
+ * Output:
+ *  dlg_regs - output DLG register struct
+ *  ttu_regs - output DLG TTU register struct
+ * Input:
+ *  e2e_pipe_param - "compacted" array of e2e pipe param struct
+ *  num_pipes - num of active "pipe" or "route"
+ *  pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
+ *  cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
+ *           Added for legacy or unrealistic timing tests.
+ */
+void dml_rq_dlg_get_dlg_reg(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+		struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
+		struct _vcs_dpi_display_e2e_pipe_params_st *e2e_pipe_param,
+		const unsigned int num_pipes,
+		const unsigned int pipe_idx,
+		const bool cstate_en,
+		const bool pstate_en,
+		const bool vm_en,
+		const bool iflip_en);
+
+/* Function: dml_rq_dlg_get_row_heights
+ *  Calculate dpte and meta row heights
+ */
+void dml_rq_dlg_get_row_heights(
+		struct display_mode_lib *mode_lib,
+		unsigned int *o_dpte_row_height,
+		unsigned int *o_meta_row_height,
+		unsigned int vp_width,
+		unsigned int data_pitch,
+		int source_format,
+		int tiling,
+		int macro_tile_size,
+		int source_scan,
+		int is_chroma);
+
+/* Function: dml_rq_dlg_get_arb_params */
+void dml_rq_dlg_get_arb_params(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_arb_params_st *arb_param);
+
+#endif

drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.h

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_RQ_DLG_HELPERS_H__
+#define __DISPLAY_RQ_DLG_HELPERS_H__
+
+#include "dml_common_defs.h"
+#include "display_mode_lib.h"
+
+/* Function: Printer functions
+ *  Print various struct
+ */
+void print__rq_params_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_rq_params_st rq_param);
+void print__data_rq_sizing_params_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_data_rq_sizing_params_st rq_sizing);
+void print__data_rq_dlg_params_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_data_rq_dlg_params_st rq_dlg_param);
+void print__data_rq_misc_params_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_data_rq_misc_params_st rq_misc_param);
+void print__rq_dlg_params_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_rq_dlg_params_st rq_dlg_param);
+void print__dlg_sys_params_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param);
+
+void print__data_rq_regs_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_data_rq_regs_st data_rq_regs);
+void print__rq_regs_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_rq_regs_st rq_regs);
+void print__dlg_regs_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_dlg_regs_st dlg_regs);
+void print__ttu_regs_st(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_ttu_regs_st ttu_regs);
+
+#endif

drivers/gpu/drm/amd/display/dc/dml/display_watermark.h

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DISPLAY_WATERMARK_H__
+#define __DISPLAY_WATERMARK_H__
+
+#include "dml_common_defs.h"
+
+struct display_mode_lib;
+
+double dml_wm_urgent_extra(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+		unsigned int num_pipes);
+double dml_wm_urgent_extra_max(struct display_mode_lib *mode_lib);
+
+double dml_wm_urgent_e2e(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes);
+double dml_wm_urgent(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+		unsigned int num_planes);
+double dml_wm_pte_meta_urgent(struct display_mode_lib *mode_lib, double urgent_wm_us);
+double dml_wm_dcfclk_deepsleep_mhz_e2e(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes);
+double dml_wm_dcfclk_deepsleep_mhz(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+		unsigned int num_planes);
+
+struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate_e2e(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes);
+struct _vcs_dpi_cstate_pstate_watermarks_st dml_wm_cstate_pstate(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+		unsigned int num_pipes);
+
+double dml_wm_writeback_pstate_e2e(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *pipes,
+		unsigned int num_pipes);
+double dml_wm_writeback_pstate(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_wm_calc_pipe_params_st *pipes,
+		unsigned int num_pipes);
+
+double dml_wm_expected_stutter_eff_e2e(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+		unsigned int num_pipes);
+double dml_wm_expected_stutter_eff_e2e_with_vblank(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+		unsigned int num_pipes);
+
+unsigned int dml_wm_e2e_to_wm(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_display_e2e_pipe_params_st *e2e,
+		unsigned int num_pipes,
+		struct _vcs_dpi_wm_calc_pipe_params_st *wm);
+
+double dml_wm_calc_total_data_read_bw(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+		unsigned int num_planes);
+double dml_wm_calc_return_bw(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_wm_calc_pipe_params_st *planes,
+		unsigned int num_planes);
+
+#endif

drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.h

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#ifndef __DC_COMMON_DEFS_H__
+#define __DC_COMMON_DEFS_H__
+
+#include "dm_services.h"
+#include "dc_features.h"
+#include "display_mode_structs.h"
+#include "display_mode_enums.h"
+
+#define DTRACE(str, ...) dm_logger_write(mode_lib->logger, LOG_DML, str, ##__VA_ARGS__);
+
+double dml_min(double a, double b);
+double dml_max(double a, double b);
+bool dml_util_is_420(enum source_format_class sorce_format);
+double dml_ceil_ex(double x, double granularity);
+double dml_floor_ex(double x, double granularity);
+double dml_log(double x, double base);
+double dml_ceil(double a);
+double dml_floor(double a);
+double dml_round(double a);
+int dml_log2(double x);
+double dml_pow(double a, int exp);
+unsigned int dml_round_to_multiple(
+			unsigned int num, unsigned int multiple, bool up);
+double dml_fmod(double f, int val);
+double dml_ceil_2(double f);
+
+#endif /* __DC_COMMON_DEFS_H__ */

drivers/gpu/drm/amd/display/dc/dml/soc_bounding_box.c

+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "soc_bounding_box.h"
+#include "display_mode_lib.h"
+
+void dml_socbb_set_latencies(
+		struct display_mode_lib *mode_lib,
+		struct _vcs_dpi_soc_bounding_box_st *from_box)
+{
+	struct _vcs_dpi_soc_bounding_box_st *to_box = &mode_lib->soc;
+
+	to_box->dram_clock_change_latency_us = from_box->dram_clock_change_latency_us;
+	to_box->sr_exit_time_us = from_box->sr_exit_time_us;
+	to_box->sr_enter_plus_exit_time_us = from_box->sr_enter_plus_exit_time_us;
+	to_box->urgent_latency_us = from_box->urgent_latency_us;
+	to_box->writeback_latency_us = from_box->writeback_latency_us;
+	DTRACE("box.dram_clock_change_latency_us: %f", from_box->dram_clock_change_latency_us);
+	DTRACE("box.sr_exit_time_us: %f", from_box->sr_exit_time_us);
+	DTRACE("box.sr_enter_plus_exit_time_us: %f", from_box->sr_enter_plus_exit_time_us);
+	DTRACE("box.urgent_latency_us: %f", from_box->urgent_latency_us);
+	DTRACE("box.writeback_latency_us: %f", from_box->writeback_latency_us);
+
+}
+
+struct _vcs_dpi_voltage_scaling_st dml_socbb_voltage_scaling(
+		struct _vcs_dpi_soc_bounding_box_st *box,
+		enum voltage_state voltage)
+{
+	switch (voltage) {
+	case dm_vmin:
+		return box->vmin;
+	case dm_vnom:
+		return box->vnom;
+	case dm_vmax:
+	default:
+		return box->vmax;
+	}
+}
+
+double dml_socbb_return_bw_mhz(struct _vcs_dpi_soc_bounding_box_st *box, enum voltage_state voltage)
+{
+	double return_bw;
+
+	struct _vcs_dpi_voltage_scaling_st state = dml_socbb_voltage_scaling(box, voltage);
+
+	return_bw = dml_min(
+			((double) box->return_bus_width_bytes) * state.dcfclk_mhz,
+			state.dram_bw_per_chan_gbps * 1000.0 * (double) box->num_chans
+					* box->ideal_dram_bw_after_urgent_percent / 100.0);
+	return return_bw;
+}