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Commit 06f06964 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'arm-soc/for-6.0/devicetree' of https://github.com/Broadcom/stblinux into arm/fixes 

This pull request contains Broadcom ARM-based SoCs Device Tree fixes for
6.0, please pull the following:

- William fixes a number of the recently submitted DTS files for 63178,
6846, 6878 to have correct PSCI node propertie as well as correct timer
CPU masks

* tag 'arm-soc/for-6.0/devicetree' of https://github.com/Broadcom/stblinux:
  ARM: dts: bcmbca: bcm6878: cosmetic change
  ARM: dts: bcmbca: bcm6878: fix timer node cpu mask flag
  ARM: dts: bcmbca: bcm6846: fix interrupt controller node
  ARM: dts: bcmbca: bcm6846: clean up psci node
  ARM: dts: bcmbca: bcm6846: fix timer node cpu mask flag
  ARM: dts: bcmbca: bcm63178: cosmetic change
  ARM: dts: bcmbca: bcm63178: fix interrupt controller node
  ARM: dts: bcmbca: bcm63178: clean up psci node
  ARM: dts: bcmbca: bcm63178: fix timer node cpu mask flag

Link: https://lore.kernel.org/r/20220829225103.753223-1-f.fainelli@gmail.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 92c7c5b0 f75fccbd
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Showing with 25 additions and 22 deletions
arch/arm/boot/dts/bcm63178.dtsi
View file @ 06f06964
...@@ -32,6 +32,7 @@ CA7_1: cpu@1 { ...@@ -32,6 +32,7 @@ CA7_1: cpu@1 {
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
enable-method = "psci"; enable-method = "psci";
}; };
CA7_2: cpu@2 { CA7_2: cpu@2 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
...@@ -39,6 +40,7 @@ CA7_2: cpu@2 { ...@@ -39,6 +40,7 @@ CA7_2: cpu@2 {
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
enable-method = "psci"; enable-method = "psci";
}; };
L2_0: l2-cache0 { L2_0: l2-cache0 {
compatible = "cache"; compatible = "cache";
}; };
...@@ -46,10 +48,10 @@ L2_0: l2-cache0 { ...@@ -46,10 +48,10 @@ L2_0: l2-cache0 {
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured; arm,cpu-registers-not-fw-configured;
}; };
...@@ -80,23 +82,23 @@ uart_clk: uart-clk { ...@@ -80,23 +82,23 @@ uart_clk: uart-clk {
psci { psci {
compatible = "arm,psci-0.2"; compatible = "arm,psci-0.2";
method = "smc"; method = "smc";
cpu_off = <1>;
cpu_on = <2>;
}; };
axi@81000000 { axi@81000000 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0x81000000 0x4000>; ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 { gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic"; compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller; interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>, reg = <0x1000 0x1000>,
<0x2000 0x2000>; <0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
}; };
}; };
......
arch/arm/boot/dts/bcm6846.dtsi
View file @ 06f06964
...@@ -40,10 +40,10 @@ L2_0: l2-cache0 { ...@@ -40,10 +40,10 @@ L2_0: l2-cache0 {
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured; arm,cpu-registers-not-fw-configured;
}; };
...@@ -65,23 +65,23 @@ periph_clk: periph-clk { ...@@ -65,23 +65,23 @@ periph_clk: periph-clk {
psci { psci {
compatible = "arm,psci-0.2"; compatible = "arm,psci-0.2";
method = "smc"; method = "smc";
cpu_off = <1>;
cpu_on = <2>;
}; };
axi@81000000 { axi@81000000 {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0x81000000 0x4000>; ranges = <0 0x81000000 0x8000>;
gic: interrupt-controller@1000 { gic: interrupt-controller@1000 {
compatible = "arm,cortex-a7-gic"; compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller; interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
reg = <0x1000 0x1000>, reg = <0x1000 0x1000>,
<0x2000 0x2000>; <0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
}; };
}; };
......
arch/arm/boot/dts/bcm6878.dtsi
View file @ 06f06964
...@@ -32,6 +32,7 @@ CA7_1: cpu@1 { ...@@ -32,6 +32,7 @@ CA7_1: cpu@1 {
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
enable-method = "psci"; enable-method = "psci";
}; };
L2_0: l2-cache0 { L2_0: l2-cache0 {
compatible = "cache"; compatible = "cache";
}; };
...@@ -39,10 +40,10 @@ L2_0: l2-cache0 { ...@@ -39,10 +40,10 @@ L2_0: l2-cache0 {
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
arm,cpu-registers-not-fw-configured; arm,cpu-registers-not-fw-configured;
}; };
......
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