Commit 0738badd authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard

ARM: dts: sun8i: r40: Add I2C pinmux options

The R40 has five I2C controllers. Currently only I2C0 has its pinmux
option defined.

Add the options for the remaining four, and set them as the default,
since each controller has only one possible pinmux configuration.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent cabbaed7
......@@ -373,6 +373,26 @@ i2c0_pins: i2c0-pins {
function = "i2c0";
};
i2c1_pins: i2c1-pins {
pins = "PB18", "PB19";
function = "i2c1";
};
i2c2_pins: i2c2-pins {
pins = "PB20", "PB21";
function = "i2c2";
};
i2c3_pins: i2c3-pins {
pins = "PI0", "PI1";
function = "i2c3";
};
i2c4_pins: i2c4-pins {
pins = "PI2", "PI3";
function = "i2c4";
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
......@@ -528,6 +548,8 @@ i2c1: i2c@1c2b000 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
......@@ -539,6 +561,8 @@ i2c2: i2c@1c2b400 {
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
......@@ -550,6 +574,8 @@ i2c3: i2c@1c2b800 {
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
......@@ -561,6 +587,8 @@ i2c4: i2c@1c2c000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C4>;
resets = <&ccu RST_BUS_I2C4>;
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
......
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