Commit 07f123de authored by Vidya Sagar's avatar Vidya Sagar Committed by Lorenzo Pieralisi

PCI: dwc: Add support to enable CDM register check

Add support to enable CDM (Configuration Dependent Module) register
check for any data corruption based on the DT property
'snps,enable-cdm-check'.
Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarGustavo Pimentel <gustavo.pimentel@synopsys.com>
parent f4e84a5d
...@@ -547,4 +547,11 @@ void dw_pcie_setup(struct dw_pcie *pci) ...@@ -547,4 +547,11 @@ void dw_pcie_setup(struct dw_pcie *pci)
break; break;
} }
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
if (of_property_read_bool(np, "snps,enable-cdm-check")) {
val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
PCIE_PL_CHK_REG_CHK_REG_START;
dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
}
} }
...@@ -86,6 +86,15 @@ ...@@ -86,6 +86,15 @@
#define PCIE_MISC_CONTROL_1_OFF 0x8BC #define PCIE_MISC_CONTROL_1_OFF 0x8BC
#define PCIE_DBI_RO_WR_EN BIT(0) #define PCIE_DBI_RO_WR_EN BIT(0)
#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20
#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0)
#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1)
#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16)
#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17)
#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18)
#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28
/* /*
* iATU Unroll-specific register definitions * iATU Unroll-specific register definitions
* From 4.80 core version the address translation will be made by unroll * From 4.80 core version the address translation will be made by unroll
......
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