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Commit 083516ad authored by Tony Lindgren's avatar Tony Lindgren
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Merge tags 'genpd-dts-dra7', 'genpd-dts-omap4' and 'genpd-dts-omap5' into omap-for-v5.13/dts-genpd 

Merge together genpd related dts changes to provide base for dropping the
legacy data to prevent merge conflicts and to send dts changes separately.
parents ecb4c5c0 e1d4a11d e1808879
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Showing with 321 additions and 167 deletions
arch/arm/boot/dts/omap4-l4.dtsi
View file @ 083516ad
// SPDX-License-Identifier: GPL-2.0
&l4_cfg { /* 0x4a000000 */
compatible = "ti,omap4-l4-cfg", "simple-bus";
compatible = "ti,omap4-l4-cfg", "simple-pm-bus";
power-domains = <&prm_core>;
clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
clock-names = "fck";
reg = <0x4a000000 0x800>,
<0x4a000800 0x800>,
<0x4a001000 0x1000>;
......@@ -16,7 +19,7 @@ &l4_cfg { /* 0x4a000000 */
<0x00300000 0x4a300000 0x080000>; /* segment 6 */
segment@0 { /* 0x4a000000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
......@@ -347,7 +350,7 @@ mmu_dsp: mmu@0 {
};
segment@80000 { /* 0x4a080000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
......@@ -639,7 +642,7 @@ hwspinlock: spinlock@0 {
};
segment@100000 { /* 0x4a100000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
......@@ -741,13 +744,13 @@ target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
};
segment@180000 { /* 0x4a180000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
};
segment@200000 { /* 0x4a200000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
......@@ -903,13 +906,13 @@ target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
};
segment@280000 { /* 0x4a280000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
};
l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
......@@ -944,7 +947,10 @@ l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
};
&l4_wkup { /* 0x4a300000 */
compatible = "ti,omap4-l4-wkup", "simple-bus";
compatible = "ti,omap4-l4-wkup", "simple-pm-bus";
power-domains = <&prm_wkup>;
clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>;
clock-names = "fck";
reg = <0x4a300000 0x800>,
<0x4a300800 0x800>,
<0x4a301000 0x1000>;
......@@ -956,7 +962,7 @@ &l4_wkup { /* 0x4a300000 */
<0x00020000 0x4a320000 0x010000>; /* segment 2 */
segment@0 { /* 0x4a300000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
......@@ -1062,7 +1068,7 @@ omap4_scm_wkup: scm@c000 {
};
segment@10000 { /* 0x4a310000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
......@@ -1231,7 +1237,7 @@ omap4_pmx_wkup: pinmux@40 {
};
segment@20000 { /* 0x4a320000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
......@@ -1284,7 +1290,10 @@ target-module@6000 { /* 0x4a326000, ap 13 28.0 */
};
&l4_per { /* 0x48000000 */
compatible = "ti,omap4-l4-per", "simple-bus";
compatible = "ti,omap4-l4-per", "simple-pm-bus";
power-domains = <&prm_l4per>;
clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>;
clock-names = "fck";
reg = <0x48000000 0x800>,
<0x48000800 0x800>,
<0x48001000 0x400>,
......@@ -1298,7 +1307,7 @@ &l4_per { /* 0x48000000 */
<0x00200000 0x48200000 0x200000>; /* segment 1 */
segment@0 { /* 0x48000000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
......@@ -2437,7 +2446,7 @@ mmc5: mmc@0 {
};
segment@200000 { /* 0x48200000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00150000 0x00350000 0x001000>, /* ap 77 */
......
arch/arm/boot/dts/omap4.dtsi
View file @ 083516ad
......@@ -59,14 +59,12 @@ cpu@1 {
};
/*
* Note that 4430 needs cross trigger interface (CTI) supported
* before we can configure the interrupts. This means sampling
* events are not supported for pmu. Note that 4460 does not use
* CTI, see also 4460.dtsi.
* Needed early by omap4_sram_init() for barrier, do not move to l3
* interconnect as simple-pm-bus probes at module_init() time.
*/
pmu {
compatible = "arm,cortex-a9-pmu";
ti,hwmods = "debugss";
ocmcram: sram@40304000 {
compatible = "mmio-sram";
reg = <0x40304000 0xa000>; /* 40k */
};
gic: interrupt-controller@48241000 {
......@@ -101,19 +99,6 @@ wakeupgen: interrupt-controller@48281000 {
interrupt-parent = <&gic>;
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
sram = <&ocmcram>;
};
};
/*
* XXX: Use a flat representation of the OMAP4 interconnect.
* The real OMAP interconnect network is quite complex.
......@@ -122,16 +107,24 @@ mpu {
* hierarchy.
*/
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
compatible = "simple-bus";
power-domains = <&prm_l4per>;
clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
<&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
<&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
reg = <0x44000000 0x1000>,
<0x44800000 0x2000>,
<0x45000000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l3-noc@44000000 {
compatible = "ti,omap4-l3-noc";
reg = <0x44000000 0x1000>,
<0x44800000 0x2000>,
<0x45000000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
l4_wkup: interconnect@4a300000 {
};
......@@ -142,12 +135,22 @@ l4_cfg: interconnect@4a000000 {
l4_per: interconnect@48000000 {
};
l4_abe: interconnect@40100000 {
target-module@48210000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
power-domains = <&prm_mpu>;
clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48210000 0x1f0000>;
mpu {
compatible = "ti,omap4-mpu";
sram = <&ocmcram>;
};
};
ocmcram: sram@40304000 {
compatible = "mmio-sram";
reg = <0x40304000 0xa000>; /* 40k */
l4_abe: interconnect@40100000 {
};
target-module@50000000 {
......@@ -203,6 +206,7 @@ target-module@52000000 {
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-delay-us = <2>;
power-domains = <&prm_cam>;
clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
......@@ -212,6 +216,27 @@ target-module@52000000 {
/* No child device binding, driver in staging */
};
/*
* Note that 4430 needs cross trigger interface (CTI) supported
* before we can configure the interrupts. This means sampling
* events are not supported for pmu. Note that 4460 does not use
* CTI, see also 4460.dtsi.
*/
target-module@54000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "debugss";
power-domains = <&prm_emu>;
clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x54000000 0x1000000>;
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
};
};
target-module@55082000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x4>,
......@@ -261,35 +286,70 @@ target-module@4012c000 {
/* No child device binding or driver in mainline */
};
dmm@4e000000 {
compatible = "ti,omap4-dmm";
reg = <0x4e000000 0x800>;
interrupts = <0 113 0x4>;
target-module@4e000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dmm";
reg = <0x4e000000 0x4>,
<0x4e000010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ranges = <0x0 0x4e000000 0x2000000>;
#size-cells = <1>;
#address-cells = <1>;
dmm@0 {
compatible = "ti,omap4-dmm";
reg = <0 0x800>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
};
};
emif1: emif@4c000000 {
compatible = "ti,emif-4d";
reg = <0x4c000000 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
target-module@4c000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "emif1";
ti,no-idle-on-init;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
reg = <0x4c000000 0x4>;
reg-names = "rev";
clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4c000000 0x1000000>;
emif1: emif@0 {
compatible = "ti,emif-4d";
reg = <0 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
};
emif2: emif@4d000000 {
compatible = "ti,emif-4d";
reg = <0x4d000000 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
target-module@4d000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "emif2";
ti,no-idle-on-init;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
reg = <0x4d000000 0x4>;
reg-names = "rev";
clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4d000000 0x1000000>;
emif2: emif@0 {
compatible = "ti,emif-4d";
reg = <0 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
};
dsp: dsp {
......@@ -440,6 +500,7 @@ sgx_module: target-module@56000000 {
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
power-domains = <&prm_gfx>;
clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
......
arch/arm/boot/dts/omap4460.dtsi
View file @ 083516ad
......@@ -26,13 +26,6 @@ cpu0: cpu@0 {
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "debugss";
};
thermal-zones {
#include "omap4-cpu-thermal.dtsi"
};
......@@ -128,4 +121,10 @@ &l4_cfg_target_0 {
<0x00030000 0x00030000 0x00010000>;
};
&pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
};
/include/ "omap446x-clocks.dtsi"
arch/arm/boot/dts/omap5-l4.dtsi
View file @ 083516ad
&l4_cfg { /* 0x4a000000 */
compatible = "ti,omap5-l4-cfg", "simple-bus";
compatible = "ti,omap5-l4-cfg", "simple-pm-bus";
power-domains = <&prm_core>;
clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
clock-names = "fck";
reg = <0x4a000000 0x800>,
<0x4a000800 0x800>,
<0x4a001000 0x1000>;
......@@ -15,7 +18,7 @@ &l4_cfg { /* 0x4a000000 */
<0x00300000 0x4a300000 0x080000>; /* segment 6 */
segment@0 { /* 0x4a000000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
......@@ -391,7 +394,7 @@ target-module@75000 { /* 0x4a075000, ap 81 32.0 */
};
segment@80000 { /* 0x4a080000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
......@@ -654,7 +657,7 @@ hwspinlock: spinlock@0 {
};
segment@100000 { /* 0x4a100000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
......@@ -691,22 +694,44 @@ target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
};
target-module@40000 { /* 0x4a140000, ap 101 16.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x400fc 4>,
<0x41100 4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
power-domains = <&prm_l3init>;
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 0>;
clock-names = "fck";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x0 0x40000 0x10000>;
sata: sata@0 {
compatible = "snps,dwc-ahci";
reg = <0 0x1100>, <0x1100 0x8>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
ports-implemented = <0x1>;
};
};
};
segment@180000 { /* 0x4a180000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
};
segment@200000 { /* 0x4a200000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
......@@ -912,20 +937,23 @@ target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
};
segment@280000 { /* 0x4a280000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
};
segment@300000 { /* 0x4a300000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
&l4_per { /* 0x48000000 */
compatible = "ti,omap5-l4-per", "simple-bus";
compatible = "ti,omap5-l4-per", "simple-pm-bus";
power-domains = <&prm_core>;
clocks = <&l4per_clkctrl OMAP5_L4_PER_CLKCTRL 0>;
clock-names = "fck";
reg = <0x48000000 0x800>,
<0x48000800 0x800>,
<0x48001000 0x400>,
......@@ -939,7 +967,7 @@ &l4_per { /* 0x48000000 */
<0x00200000 0x48200000 0x200000>; /* segment 1 */
segment@0 { /* 0x48000000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
......@@ -2148,14 +2176,17 @@ mmc5: mmc@0 {
};
segment@200000 { /* 0x48200000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
};
};
&l4_wkup { /* 0x4ae00000 */
compatible = "ti,omap5-l4-wkup", "simple-bus";
compatible = "ti,omap5-l4-wkup", "simple-pm-bus";
power-domains = <&prm_wkupaon>;
clocks = <&wkupaon_clkctrl OMAP5_L4_WKUP_CLKCTRL 0>;
clock-names = "fck";
reg = <0x4ae00000 0x800>,
<0x4ae00800 0x800>,
<0x4ae01000 0x1000>;
......@@ -2167,7 +2198,7 @@ &l4_wkup { /* 0x4ae00000 */
<0x00020000 0x4ae20000 0x010000>; /* segment 2 */
segment@0 { /* 0x4ae00000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
......@@ -2296,7 +2327,7 @@ scm_wkup_pad_conf_clocks: clocks@0 {
};
segment@10000 { /* 0x4ae10000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
......@@ -2423,7 +2454,7 @@ keypad: keypad@0 {
};
segment@20000 { /* 0x4ae20000 */
compatible = "simple-bus";
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
......
arch/arm/boot/dts/omap5.dtsi
View file @ 083516ad
......@@ -106,6 +106,15 @@ pmu {
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
};
/*
* Needed early by omap4_sram_init() for barrier, do not move to l3
* interconnect as simple-pm-bus probes at module_init() time.
*/
ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0 0x40300000 0 0x20000>; /* 128k */
};
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
......@@ -125,19 +134,6 @@ wakeupgen: interrupt-controller@48281000 {
interrupt-parent = <&gic>;
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
sram = <&ocmcram>;
};
};
/*
* XXX: Use a flat representation of the OMAP3 interconnect.
* The real OMAP interconnect network is quite complex.
......@@ -146,17 +142,25 @@ mpu {
* hierarchy.
*/
ocp {
compatible = "ti,omap5-l3-noc", "simple-bus";
compatible = "simple-pm-bus";
power-domains = <&prm_core>;
clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>,
<&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>,
<&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xc0000000>;
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
reg = <0 0x44000000 0 0x2000>,
<0 0x44800000 0 0x3000>,
<0 0x45000000 0 0x4000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l3-noc@44000000 {
compatible = "ti,omap5-l3-noc";
reg = <0x44000000 0x2000>,
<0x44800000 0x3000>,
<0x45000000 0x4000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
l4_wkup: interconnect@4ae00000 {
};
......@@ -167,31 +171,58 @@ l4_cfg: interconnect@4a000000 {
l4_per: interconnect@48000000 {
};
l4_abe: interconnect@40100000 {
target-module@48210000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
power-domains = <&prm_mpu>;
clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48210000 0x1f0000>;
mpu {
compatible = "ti,omap4-mpu";
sram = <&ocmcram>;
};
};
ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x20000>; /* 128k */
l4_abe: interconnect@40100000 {
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 4>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
clocks = <&l3_iclk_div>;
target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000000 4>,
<0x50000010 4>,
<0x50000014 4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
ti,no-idle-on-init;
clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
<0x00000000 0x00000000 0x40000000>; /* data */
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 4>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
};
target-module@55082000 {
......@@ -246,35 +277,70 @@ ipu: ipu@55020000 {
status = "disabled";
};
dmm@4e000000 {
compatible = "ti,omap5-dmm";
reg = <0x4e000000 0x800>;
interrupts = <0 113 0x4>;
target-module@4e000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dmm";
reg = <0x4e000000 0x4>,
<0x4e000010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ranges = <0x0 0x4e000000 0x2000000>;
#size-cells = <1>;
#address-cells = <1>;
dmm@0 {
compatible = "ti,omap5-dmm";
reg = <0 0x800>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
};
};
emif1: emif@4c000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif1";
ti,no-idle-on-init;
phy-type = <2>; /* DDR PHY type: Intelli PHY */
reg = <0x4c000000 0x400>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
target-module@4c000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "emif1";
reg = <0x4c000000 0x4>;
reg-names = "rev";
clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4c000000 0x1000000>;
emif1: emif@0 {
compatible = "ti,emif-4d5";
reg = <0 0x400>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
phy-type = <2>; /* DDR PHY type: Intelli PHY */
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
};
emif2: emif@4d000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif2";
ti,no-idle-on-init;
phy-type = <2>; /* DDR PHY type: Intelli PHY */
reg = <0x4d000000 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
target-module@4d000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
ti,hwmods = "emif2";
reg = <0x4d000000 0x4>;
reg-names = "rev";
clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
clock-names = "fck";
ti,no-idle;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4d000000 0x1000000>;
emif2: emif@0 {
compatible = "ti,emif-4d5";
reg = <0 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
phy-type = <2>; /* DDR PHY type: Intelli PHY */
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
};
aes1_target: target-module@4b501000 {
......@@ -374,18 +440,6 @@ bandgap: bandgap@4a0021e0 {
#thermal-sensor-cells = <1>;
};
/* OCP2SCP3 */
sata: sata@4a141100 {
compatible = "snps,dwc-ahci";
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
......
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