Commit 0940605a authored by Sean Wang's avatar Sean Wang Committed by Felix Fietkau

mt76: mt7921: fixup rx bitrate statistics

Since the related rx bitrate fields have been moved to group3 in Rxv,
fix rx bitrate statistics in mt7921_mac_fill_rx routine.

Fixes: 163f4d22 ("mt76: mt7921: add MAC support")
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent a7e3033f
...@@ -400,7 +400,9 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb) ...@@ -400,7 +400,9 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb)
/* RXD Group 3 - P-RXV */ /* RXD Group 3 - P-RXV */
if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
u32 v0, v1, v2; u8 stbc, gi;
u32 v0, v1;
bool cck;
rxv = rxd; rxv = rxd;
rxd += 2; rxd += 2;
...@@ -409,7 +411,6 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb) ...@@ -409,7 +411,6 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb)
v0 = le32_to_cpu(rxv[0]); v0 = le32_to_cpu(rxv[0]);
v1 = le32_to_cpu(rxv[1]); v1 = le32_to_cpu(rxv[1]);
v2 = le32_to_cpu(rxv[2]);
if (v0 & MT_PRXV_HT_AD_CODE) if (v0 & MT_PRXV_HT_AD_CODE)
status->enc_flags |= RX_ENC_FLAG_LDPC; status->enc_flags |= RX_ENC_FLAG_LDPC;
...@@ -429,87 +430,87 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb) ...@@ -429,87 +430,87 @@ int mt7921_mac_fill_rx(struct mt7921_dev *dev, struct sk_buff *skb)
status->chain_signal[i]); status->chain_signal[i]);
} }
/* RXD Group 5 - C-RXV */ stbc = FIELD_GET(MT_PRXV_STBC, v0);
if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { gi = FIELD_GET(MT_PRXV_SGI, v0);
u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2); cck = false;
u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
bool cck = false;
rxd += 18; idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
if ((u8 *)rxd - skb->data >= skb->len) mode = FIELD_GET(MT_PRXV_TX_MODE, v0);
return -EINVAL;
idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0); switch (mode) {
mode = FIELD_GET(MT_CRXV_TX_MODE, v2); case MT_PHY_TYPE_CCK:
cck = true;
switch (mode) { fallthrough;
case MT_PHY_TYPE_CCK: case MT_PHY_TYPE_OFDM:
cck = true; i = mt76_get_rate(&dev->mt76, sband, i, cck);
fallthrough; break;
case MT_PHY_TYPE_OFDM: case MT_PHY_TYPE_HT_GF:
i = mt76_get_rate(&dev->mt76, sband, i, cck); case MT_PHY_TYPE_HT:
break; status->encoding = RX_ENC_HT;
case MT_PHY_TYPE_HT_GF: if (i > 31)
case MT_PHY_TYPE_HT:
status->encoding = RX_ENC_HT;
if (i > 31)
return -EINVAL;
break;
case MT_PHY_TYPE_VHT:
status->nss =
FIELD_GET(MT_PRXV_NSTS, v0) + 1;
status->encoding = RX_ENC_VHT;
if (i > 9)
return -EINVAL;
break;
case MT_PHY_TYPE_HE_MU:
status->flag |= RX_FLAG_RADIOTAP_HE_MU;
fallthrough;
case MT_PHY_TYPE_HE_SU:
case MT_PHY_TYPE_HE_EXT_SU:
case MT_PHY_TYPE_HE_TB:
status->nss =
FIELD_GET(MT_PRXV_NSTS, v0) + 1;
status->encoding = RX_ENC_HE;
status->flag |= RX_FLAG_RADIOTAP_HE;
i &= GENMASK(3, 0);
if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
status->he_gi = gi;
status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
break;
default:
return -EINVAL; return -EINVAL;
} break;
status->rate_idx = i; case MT_PHY_TYPE_VHT:
status->nss =
switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) { FIELD_GET(MT_PRXV_NSTS, v0) + 1;
case IEEE80211_STA_RX_BW_20: status->encoding = RX_ENC_VHT;
break; if (i > 9)
case IEEE80211_STA_RX_BW_40:
if (mode & MT_PHY_TYPE_HE_EXT_SU &&
(idx & MT_PRXV_TX_ER_SU_106T)) {
status->bw = RATE_INFO_BW_HE_RU;
status->he_ru =
NL80211_RATE_INFO_HE_RU_ALLOC_106;
} else {
status->bw = RATE_INFO_BW_40;
}
break;
case IEEE80211_STA_RX_BW_80:
status->bw = RATE_INFO_BW_80;
break;
case IEEE80211_STA_RX_BW_160:
status->bw = RATE_INFO_BW_160;
break;
default:
return -EINVAL; return -EINVAL;
break;
case MT_PHY_TYPE_HE_MU:
status->flag |= RX_FLAG_RADIOTAP_HE_MU;
fallthrough;
case MT_PHY_TYPE_HE_SU:
case MT_PHY_TYPE_HE_EXT_SU:
case MT_PHY_TYPE_HE_TB:
status->nss =
FIELD_GET(MT_PRXV_NSTS, v0) + 1;
status->encoding = RX_ENC_HE;
status->flag |= RX_FLAG_RADIOTAP_HE;
i &= GENMASK(3, 0);
if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
status->he_gi = gi;
status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
break;
default:
return -EINVAL;
}
status->rate_idx = i;
switch (FIELD_GET(MT_PRXV_FRAME_MODE, v0)) {
case IEEE80211_STA_RX_BW_20:
break;
case IEEE80211_STA_RX_BW_40:
if (mode & MT_PHY_TYPE_HE_EXT_SU &&
(idx & MT_PRXV_TX_ER_SU_106T)) {
status->bw = RATE_INFO_BW_HE_RU;
status->he_ru =
NL80211_RATE_INFO_HE_RU_ALLOC_106;
} else {
status->bw = RATE_INFO_BW_40;
} }
break;
case IEEE80211_STA_RX_BW_80:
status->bw = RATE_INFO_BW_80;
break;
case IEEE80211_STA_RX_BW_160:
status->bw = RATE_INFO_BW_160;
break;
default:
return -EINVAL;
}
status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
if (mode < MT_PHY_TYPE_HE_SU && gi)
status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc; if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
if (mode < MT_PHY_TYPE_HE_SU && gi) rxd += 18;
status->enc_flags |= RX_ENC_FLAG_SHORT_GI; if ((u8 *)rxd - skb->data >= skb->len)
return -EINVAL;
} }
} }
......
...@@ -97,18 +97,24 @@ enum rx_pkt_type { ...@@ -97,18 +97,24 @@ enum rx_pkt_type {
#define MT_RXD3_NORMAL_PF_MODE BIT(29) #define MT_RXD3_NORMAL_PF_MODE BIT(29)
#define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30) #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
/* P-RXV */ /* P-RXV DW0 */
#define MT_PRXV_TX_RATE GENMASK(6, 0) #define MT_PRXV_TX_RATE GENMASK(6, 0)
#define MT_PRXV_TX_DCM BIT(4) #define MT_PRXV_TX_DCM BIT(4)
#define MT_PRXV_TX_ER_SU_106T BIT(5) #define MT_PRXV_TX_ER_SU_106T BIT(5)
#define MT_PRXV_NSTS GENMASK(9, 7) #define MT_PRXV_NSTS GENMASK(9, 7)
#define MT_PRXV_HT_AD_CODE BIT(11) #define MT_PRXV_HT_AD_CODE BIT(11)
#define MT_PRXV_FRAME_MODE GENMASK(14, 12)
#define MT_PRXV_SGI GENMASK(16, 15)
#define MT_PRXV_STBC GENMASK(23, 22)
#define MT_PRXV_TX_MODE GENMASK(27, 24)
#define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28) #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
#define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
/* P-RXV DW1 */
#define MT_PRXV_RCPI3 GENMASK(31, 24) #define MT_PRXV_RCPI3 GENMASK(31, 24)
#define MT_PRXV_RCPI2 GENMASK(23, 16) #define MT_PRXV_RCPI2 GENMASK(23, 16)
#define MT_PRXV_RCPI1 GENMASK(15, 8) #define MT_PRXV_RCPI1 GENMASK(15, 8)
#define MT_PRXV_RCPI0 GENMASK(7, 0) #define MT_PRXV_RCPI0 GENMASK(7, 0)
#define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
/* C-RXV */ /* C-RXV */
#define MT_CRXV_HT_STBC GENMASK(1, 0) #define MT_CRXV_HT_STBC GENMASK(1, 0)
......
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