drm/amdgpu: enable RAS support for sienna cichlid

enabled GECC error injection and query support
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

@@ -1965,8 +1965,9 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
 	*supported = 0;
 
 	if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
-	    (adev->asic_type != CHIP_VEGA20 &&
-	     adev->asic_type != CHIP_ARCTURUS))
+	    (adev->asic_type != CHIP_VEGA20   &&
+	     adev->asic_type != CHIP_ARCTURUS &&
+	     adev->asic_type != CHIP_SIENNA_CICHLID))
 		return;
 
 	if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

@@ -633,6 +633,10 @@ static int gmc_v10_0_late_init(void *handle)
 	if (r)
 		return r;
 
+	r = amdgpu_gmc_ras_late_init(adev);
+	if (r)
+		return r;
+
 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 }