Commit 0b0d4be6 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "This is a sort of random collection of clk fixes that have come in
  since the merge window:

   - Handful of memory allocation and potentially bad pointer usage
     fixes

   - JSON format was incorrect for clk_dump because it missed a comma

   - Two Kconfig fixes, one duplicate and one missing select line

   - Compiler warning fix for the VC5 clk driver

   - Name and rate fixes for PLLs in the stratix10 driver so it can
     properly detect PLL rates and parents"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: socfpga: stratix10: fix naming convention for the fixed-clocks
  clk: socfpga: stratix10: fix rate calculation for pll clocks
  clk: qcom: Select QCOM_GDSC with MSM_GCC_8998
  clk: vc5: Abort clock configuration without upstream clock
  clk: sysfs: fix invalid JSON in clk_dump
  clk: imx: Remove Kconfig duplicate include
  clk: zynqmp: Fix memory allocation in zynqmp_clk_setup
  clk: tegra: dfll: Fix a potential Oop in remove()
  clk: imx: fix potential NULL dereference in imx8qxp_lpcg_clk_probe()
parents 8f45fa27 b488517b
......@@ -293,7 +293,6 @@ config COMMON_CLK_BD718XX
source "drivers/clk/actions/Kconfig"
source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/imgtec/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/ingenic/Kconfig"
......
......@@ -262,8 +262,10 @@ static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
src = VC5_PRIM_SRC_SHDN_EN_XTAL;
if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
else /* Invalid; should have been caught by vc5_probe() */
return -EINVAL;
}
return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
......
......@@ -2779,7 +2779,7 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
seq_printf(s, "\"protect_count\": %d,", c->protect_count);
seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));
seq_printf(s, "\"duty_cycle\": %u",
clk_core_get_scaled_duty_cycle(c, 100000));
}
......
......@@ -169,6 +169,8 @@ static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev)
return -ENODEV;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -EINVAL;
base = devm_ioremap(dev, res->start, resource_size(res));
if (!base)
return -ENOMEM;
......
......@@ -215,6 +215,7 @@ config MSM_MMCC_8996
config MSM_GCC_8998
tristate "MSM8998 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on msm8998 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
......
......@@ -43,7 +43,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
/* Read mdiv and fdiv from the fdbck register */
reg = readl(socfpgaclk->hw.reg + 0x4);
mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
return (unsigned long)vco_freq;
}
......
......@@ -12,17 +12,17 @@
#include "stratix10-clk.h"
static const char * const pll_mux[] = { "osc1", "cb_intosc_hs_div2_clk",
"f2s_free_clk",};
static const char * const pll_mux[] = { "osc1", "cb-intosc-hs-div2-clk",
"f2s-free-clk",};
static const char * const cntr_mux[] = { "main_pll", "periph_pll",
"osc1", "cb_intosc_hs_div2_clk",
"f2s_free_clk"};
static const char * const boot_mux[] = { "osc1", "cb_intosc_hs_div2_clk",};
"osc1", "cb-intosc-hs-div2-clk",
"f2s-free-clk"};
static const char * const boot_mux[] = { "osc1", "cb-intosc-hs-div2-clk",};
static const char * const noc_free_mux[] = {"main_noc_base_clk",
"peri_noc_base_clk",
"osc1", "cb_intosc_hs_div2_clk",
"f2s_free_clk"};
"osc1", "cb-intosc-hs-div2-clk",
"f2s-free-clk"};
static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"};
static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"};
......@@ -33,14 +33,14 @@ static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"
static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"};
static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",};
static const char * const s2f_usr0_mux[] = {"f2s_free_clk", "boot_clk"};
static const char * const s2f_usr0_mux[] = {"f2s-free-clk", "boot_clk"};
static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"};
static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"};
static const char * const mpu_free_mux[] = {"main_mpu_base_clk",
"peri_mpu_base_clk",
"osc1", "cb_intosc_hs_div2_clk",
"f2s_free_clk"};
"osc1", "cb-intosc-hs-div2-clk",
"f2s-free-clk"};
/* clocks in AO (always on) controller */
static const struct stratix10_pll_clock s10_pll_clks[] = {
......
......@@ -133,9 +133,11 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
struct tegra_dfll_soc_data *soc;
soc = tegra_dfll_unregister(pdev);
if (IS_ERR(soc))
if (IS_ERR(soc)) {
dev_err(&pdev->dev, "failed to unregister DFLL: %ld\n",
PTR_ERR(soc));
return PTR_ERR(soc);
}
tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
......
......@@ -669,8 +669,8 @@ static int zynqmp_clk_setup(struct device_node *np)
if (ret)
return ret;
zynqmp_data = kzalloc(sizeof(*zynqmp_data) + sizeof(*zynqmp_data) *
clock_max_idx, GFP_KERNEL);
zynqmp_data = kzalloc(struct_size(zynqmp_data, hws, clock_max_idx),
GFP_KERNEL);
if (!zynqmp_data)
return -ENOMEM;
......
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