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Commit 0c5c62dd authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'pci-v5.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull pci updates from Bjorn Helgaas:
 "Enumeration:
   - Conserve IRQs by setting up portdrv IRQs only when there are users
     (Jan Kiszka)
   - Rework and simplify _OSC negotiation for control of PCIe features
     (Joerg Roedel)
   - Remove struct pci_dev.driver pointer since it's redundant with the
     struct device.driver pointer (Uwe Kleine-König)

  Resource management:
   - Coalesce contiguous host bridge apertures from _CRS to accommodate
     BARs that cover more than one aperture (Kai-Heng Feng)

  Sysfs:
   - Check CAP_SYS_ADMIN before parsing user input (Krzysztof
     Wilczyński)
   - Return -EINVAL consistently from "store" functions (Krzysztof
     Wilczyński)
   - Use sysfs_emit() in endpoint "show" functions to avoid buffer
     overruns (Kunihiko Hayashi)

  PCIe native device hotplug:
   - Ignore Link Down/Up caused by resets during error recovery so
     endpoint drivers can remain bound to the device (Lukas Wunner)

  Virtualization:
   - Avoid bus resets on Atheros QCA6174, where they hang the device
     (Ingmar Klein)
   - Work around Pericom PI7C9X2G switch packet drop erratum by using
     store and forward mode instead of cut-through (Nathan Rossi)
   - Avoid trying to enable AtomicOps on VFs; the PF setting applies to
     all VFs (Selvin Xavier)

  MSI:
   - Document that /sys/bus/pci/devices/.../irq contains the legacy INTx
     interrupt or the IRQ of the first MSI (not MSI-X) vector (Barry
     Song)

  VPD:
   - Add pci_read_vpd_any() and pci_write_vpd_any() to access anywhere
     in the possible VPD space; use these to simplify the cxgb3 driver
     (Heiner Kallweit)

  Peer-to-peer DMA:
   - Add (not subtract) the bus offset when calculating DMA address
     (Wang Lu)

  ASPM:
   - Re-enable LTR at Downstream Ports so they don't report Unsupported
     Requests when reset or hot-added devices send LTR messages
     (Mingchuang Qiao)

  Apple PCIe controller driver:
   - Add driver for Apple M1 PCIe controller (Alyssa Rosenzweig, Marc
     Zyngier)

  Cadence PCIe controller driver:
   - Return success when probe succeeds instead of falling into error
     path (Li Chen)

  HiSilicon Kirin PCIe controller driver:
   - Reorganize PHY logic and add support for external PHY drivers
     (Mauro Carvalho Chehab)
   - Support PERST# GPIOs for HiKey970 external PEX 8606 bridge (Mauro
     Carvalho Chehab)
   - Add Kirin 970 support (Mauro Carvalho Chehab)
   - Make driver removable (Mauro Carvalho Chehab)

  Intel VMD host bridge driver:
   - If IOMMU supports interrupt remapping, leave VMD MSI-X remapping
     enabled (Adrian Huang)
   - Number each controller so we can tell them apart in
     /proc/interrupts (Chunguang Xu)
   - Avoid building on UML because VMD depends on x86 bare metal APIs
     (Johannes Berg)

  Marvell Aardvark PCIe controller driver:
   - Define macros for PCI_EXP_DEVCTL_PAYLOAD_* (Pali Rohár)
   - Set Max Payload Size to 512 bytes per Marvell spec (Pali Rohár)
   - Downgrade PIO Response Status messages to debug level (Marek Behún)
   - Preserve CRS SV (Config Request Retry Software Visibility) bit in
     emulated Root Control register (Pali Rohár)
   - Fix issue in configuring reference clock (Pali Rohár)
   - Don't clear status bits for masked interrupts (Pali Rohár)
   - Don't mask unused interrupts (Pali Rohár)
   - Avoid code repetition in advk_pcie_rd_conf() (Marek Behún)
   - Retry config accesses on CRS response (Pali Rohár)
   - Simplify emulated Root Capabilities initialization (Pali Rohár)
   - Fix several link training issues (Pali Rohár)
   - Fix link-up checking via LTSSM (Pali Rohár)
   - Fix reporting of Data Link Layer Link Active (Pali Rohár)
   - Fix emulation of W1C bits (Marek Behún)
   - Fix MSI domain .alloc() method to return zero on success (Marek
     Behún)
   - Read entire 16-bit MSI vector in MSI handler, not just low 8 bits
     (Marek Behún)
   - Clear Root Port I/O Space, Memory Space, and Bus Master Enable bits
     at startup; PCI core will set those as necessary (Pali Rohár)
   - When operating as a Root Port, set class code to "PCI Bridge"
     instead of the default "Mass Storage Controller" (Pali Rohár)
   - Add emulation for PCI_BRIDGE_CTL_BUS_RESET since aardvark doesn't
     implement this per spec (Pali Rohár)
   - Add emulation of option ROM BAR since aardvark doesn't implement
     this per spec (Pali Rohár)

  MediaTek MT7621 PCIe controller driver:
   - Add MediaTek MT7621 PCIe host controller driver and DT binding
     (Sergio Paracuellos)

  Qualcomm PCIe controller driver:
   - Add SC8180x compatible string (Bjorn Andersson)
   - Add endpoint controller driver and DT binding (Manivannan
     Sadhasivam)
   - Restructure to use of_device_get_match_data() (Prasad Malisetty)
   - Add SC7280-specific pcie_1_pipe_clk_src handling (Prasad Malisetty)

  Renesas R-Car PCIe controller driver:
   - Remove unnecessary includes (Geert Uytterhoeven)

  Rockchip DesignWare PCIe controller driver:
   - Add DT binding (Simon Xue)

  Socionext UniPhier Pro5 controller driver:
   - Serialize INTx masking/unmasking (Kunihiko Hayashi)

  Synopsys DesignWare PCIe controller driver:
   - Run dwc .host_init() method before registering MSI interrupt
     handler so we can deal with pending interrupts left by bootloader
     (Bjorn Andersson)
   - Clean up Kconfig dependencies (Andy Shevchenko)
   - Export symbols to allow more modular drivers (Luca Ceresoli)

  TI DRA7xx PCIe controller driver:
   - Allow host and endpoint drivers to be modules (Luca Ceresoli)
   - Enable external clock if present (Luca Ceresoli)

  TI J721E PCIe driver:
   - Disable PHY when probe fails after initializing it (Christophe
     JAILLET)

  MicroSemi Switchtec management driver:
   - Return error to application when command execution fails because an
     out-of-band reset has cleared the device BARs, Memory Space Enable,
     etc (Kelvin Cao)
   - Fix MRPC error status handling issue (Kelvin Cao)
   - Mask out other bits when reading of management VEP instance ID
     (Kelvin Cao)
   - Return EOPNOTSUPP instead of ENOTSUPP from sysfs show functions
     (Kelvin Cao)
   - Add check of event support (Logan Gunthorpe)

  Miscellaneous:
   - Remove unused pci_pool wrappers, which have been replaced by
     dma_pool (Cai Huoqing)
   - Use 'unsigned int' instead of bare 'unsigned' (Krzysztof
     Wilczyński)
   - Use kstrtobool() directly, sans strtobool() wrapper (Krzysztof
     Wilczyński)
   - Fix some sscanf(), sprintf() format mismatches (Krzysztof
     Wilczyński)
   - Update PCI subsystem information in MAINTAINERS (Krzysztof
     Wilczyński)
   - Correct some misspellings (Krzysztof Wilczyński)"

* tag 'pci-v5.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (137 commits)
  PCI: Add ACS quirk for Pericom PI7C9X2G switches
  PCI: apple: Configure RID to SID mapper on device addition
  iommu/dart: Exclude MSI doorbell from PCIe device IOVA range
  PCI: apple: Implement MSI support
  PCI: apple: Add INTx and per-port interrupt support
  PCI: kirin: Allow removing the driver
  PCI: kirin: De-init the dwc driver
  PCI: kirin: Disable clkreq during poweroff sequence
  PCI: kirin: Move the power-off code to a common routine
  PCI: kirin: Add power_off support for Kirin 960 PHY
  PCI: kirin: Allow building it as a module
  PCI: kirin: Add MODULE_* macros
  PCI: kirin: Add Kirin 970 compatible
  PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge
  PCI: apple: Set up reference clocks when probing
  PCI: apple: Add initial hardware bring-up
  PCI: of: Allow matching of an interrupt-map local to a PCI device
  of/irq: Allow matching of an interrupt-map local to an interrupt controller
  irqdomain: Make of_phandle_args_to_fwspec() generally available
  PCI: Do not enable AtomicOps on VFs
  ...
parents 512b7931 dda4b381
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Documentation/ABI/testing/sysfs-bus-pci
View file @ 0c5c62dd
......@@ -100,6 +100,17 @@ Description:
This attribute indicates the mode that the irq vector named by
the file is in (msi vs. msix)
What: /sys/bus/pci/devices/.../irq
Date: August 2021
Contact: Linux PCI developers <linux-pci@vger.kernel.org>
Description:
If a driver has enabled MSI (not MSI-X), "irq" contains the
IRQ of the first MSI vector. Otherwise "irq" contains the
IRQ of the legacy INTx interrupt.
"irq" being set to 0 indicates that the device isn't
capable of generating legacy INTx interrupts.
What: /sys/bus/pci/devices/.../remove
Date: January 2009
Contact: Linux PCI developers <linux-pci@vger.kernel.org>
......
Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml 0 → 100644
View file @ 0c5c62dd
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT7621 PCIe controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |+
MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
properties:
compatible:
const: mediatek,mt7621-pci
reg:
items:
- description: host-pci bridge registers
- description: pcie port 0 RC control registers
- description: pcie port 1 RC control registers
- description: pcie port 2 RC control registers
ranges:
maxItems: 2
patternProperties:
'pcie@[0-2],0':
type: object
$ref: /schemas/pci/pci-bus.yaml#
properties:
resets:
maxItems: 1
clocks:
maxItems: 1
phys:
maxItems: 1
required:
- "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
- resets
- clocks
- phys
- phy-names
- ranges
unevaluatedProperties: false
required:
- compatible
- reg
- ranges
- "#interrupt-cells"
- interrupt-map-mask
- interrupt-map
- reset-gpios
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/mips-gic.h>
pcie: pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
reg = <0x1e140000 0x100>,
<0x1e142000 0x100>,
<0x1e143000 0x100>,
<0x1e144000 0x100>;
#address-cells = <3>;
#size-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
device_type = "pci";
ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
<0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
#interrupt-cells = <1>;
interrupt-map-mask = <0xF800 0 0 0>;
interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstctrl 24>;
clocks = <&clkctrl 24>;
phys = <&pcie0_phy 1>;
phy-names = "pcie-phy0";
ranges;
};
pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstctrl 25>;
clocks = <&clkctrl 25>;
phys = <&pcie0_phy 1>;
phy-names = "pcie-phy1";
ranges;
};
pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rstctrl 26>;
clocks = <&clkctrl 26>;
phys = <&pcie2_phy 0>;
phy-names = "pcie-phy2";
ranges;
};
};
...
Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml 0 → 100644
View file @ 0c5c62dd
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PCIe Endpoint Controller binding
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
allOf:
- $ref: "pci-ep.yaml#"
properties:
compatible:
const: qcom,sdx55-pcie-ep
reg:
items:
- description: Qualcomm-specific PARF configuration registers
- description: DesignWare PCIe registers
- description: External local bus interface registers
- description: Address Translation Unit (ATU) registers
- description: Memory region used to map remote RC address space
- description: BAR memory region
reg-names:
items:
- const: parf
- const: dbi
- const: elbi
- const: atu
- const: addr_space
- const: mmio
clocks:
items:
- description: PCIe Auxiliary clock
- description: PCIe CFG AHB clock
- description: PCIe Master AXI clock
- description: PCIe Slave AXI clock
- description: PCIe Slave Q2A AXI clock
- description: PCIe Sleep clock
- description: PCIe Reference clock
clock-names:
items:
- const: aux
- const: cfg
- const: bus_master
- const: bus_slave
- const: slave_q2a
- const: sleep
- const: ref
qcom,perst-regs:
description: Reference to a syscon representing TCSR followed by the two
offsets within syscon for Perst enable and Perst separation
enable registers
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
minItems: 3
maxItems: 3
interrupts:
items:
- description: PCIe Global interrupt
- description: PCIe Doorbell interrupt
interrupt-names:
items:
- const: global
- const: doorbell
reset-gpios:
description: GPIO used as PERST# input signal
maxItems: 1
wake-gpios:
description: GPIO used as WAKE# output signal
maxItems: 1
resets:
maxItems: 1
reset-names:
const: core
power-domains:
maxItems: 1
phys:
maxItems: 1
phy-names:
const: pciephy
num-lanes:
default: 2
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- qcom,perst-regs
- interrupts
- interrupt-names
- reset-gpios
- resets
- reset-names
- power-domains
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdx55.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pcie_ep: pcie-ep@40000000 {
compatible = "qcom,sdx55-pcie-ep";
reg = <0x01c00000 0x3000>,
<0x40000000 0xf1d>,
<0x40000f20 0xc8>,
<0x40001000 0x1000>,
<0x40002000 0x1000>,
<0x01c03000 0x3000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
"mmio";
clocks = <&gcc GCC_PCIE_AUX_CLK>,
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_SLV_AXI_CLK>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>;
clock-names = "aux", "cfg", "bus_master", "bus_slave",
"slave_q2a", "sleep", "ref";
qcom,perst-regs = <&tcsr 0xb258 0xb270>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global", "doorbell";
reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_PCIE_BCR>;
reset-names = "core";
power-domains = <&gcc PCIE_GDSC>;
phys = <&pcie0_lane>;
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
};
Documentation/devicetree/bindings/pci/qcom,pcie.txt
View file @ 0c5c62dd
......@@ -12,6 +12,7 @@
- "qcom,pcie-ipq4019" for ipq4019
- "qcom,pcie-ipq8074" for ipq8074
- "qcom,pcie-qcs404" for qcs404
- "qcom,pcie-sc8180x" for sc8180x
- "qcom,pcie-sdm845" for sdm845
- "qcom,pcie-sm8250" for sm8250
- "qcom,pcie-ipq6018" for ipq6018
......@@ -156,7 +157,7 @@
- "pipe" PIPE clock
- clock-names:
Usage: required for sm8250
Usage: required for sc8180x and sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "aux" Auxiliary clock
......@@ -245,7 +246,7 @@
- "ahb" AHB reset
- reset-names:
Usage: required for sdm845 and sm8250
Usage: required for sc8180x, sdm845 and sm8250
Value type: <stringlist>
Definition: Should contain the following entries
- "pci" PCIe core reset
......
Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml 0 → 100644
View file @ 0c5c62dd
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DesignWare based PCIe controller on Rockchip SoCs
maintainers:
- Shawn Lin <shawn.lin@rock-chips.com>
- Simon Xue <xxm@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
description: |+
RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
PCIe IP and thus inherits all the common properties defined in
designware-pcie.txt.
allOf:
- $ref: /schemas/pci/pci-bus.yaml#
# We need a select here so we don't match all nodes with 'snps,dw-pcie'
select:
properties:
compatible:
contains:
const: rockchip,rk3568-pcie
required:
- compatible
properties:
compatible:
items:
- const: rockchip,rk3568-pcie
- const: snps,dw-pcie
reg:
items:
- description: Data Bus Interface (DBI) registers
- description: Rockchip designed configuration registers
- description: Config registers
reg-names:
items:
- const: dbi
- const: apb
- const: config
clocks:
items:
- description: AHB clock for PCIe master
- description: AHB clock for PCIe slave
- description: AHB clock for PCIe dbi
- description: APB clock for PCIe
- description: Auxiliary clock for PCIe
clock-names:
items:
- const: aclk_mst
- const: aclk_slv
- const: aclk_dbi
- const: pclk
- const: aux
msi-map: true
num-lanes: true
phys:
maxItems: 1
phy-names:
const: pcie-phy
power-domains:
maxItems: 1
ranges:
maxItems: 2
resets:
maxItems: 1
reset-names:
const: pipe
vpcie3v3-supply: true
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- msi-map
- num-lanes
- phys
- phy-names
- power-domains
- resets
- reset-names
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
pcie3x2: pcie@fe280000 {
compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
reg = <0x3 0xc0800000 0x0 0x390000>,
<0x0 0xfe280000 0x0 0x10000>,
<0x3 0x80000000 0x0 0x100000>;
reg-names = "dbi", "apb", "config";
bus-range = <0x20 0x2f>;
clocks = <&cru 143>, <&cru 144>,
<&cru 145>, <&cru 146>,
<&cru 147>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk",
"aux";
device_type = "pci";
linux,pci-domain = <2>;
max-link-speed = <2>;
msi-map = <0x2000 &its 0x2000 0x1000>;
num-lanes = <2>;
phys = <&pcie30phy>;
phy-names = "pcie-phy";
power-domains = <&power 15>;
ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
<0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
resets = <&cru 193>;
reset-names = "pipe";
#address-cells = <3>;
#size-cells = <2>;
};
};
...
MAINTAINERS
View file @ 0c5c62dd
......@@ -1297,6 +1297,13 @@ S: Maintained
F: Documentation/devicetree/bindings/iommu/apple,dart.yaml
F: drivers/iommu/apple-dart.c
APPLE PCIE CONTROLLER DRIVER
M: Alyssa Rosenzweig <alyssa@rosenzweig.io>
M: Marc Zyngier <maz@kernel.org>
L: linux-pci@vger.kernel.org
S: Maintained
F: drivers/pci/controller/pcie-apple.c
APPLE SMC DRIVER
M: Henrik Rydberg <rydberg@bitmath.org>
L: linux-hwmon@vger.kernel.org
......@@ -12005,6 +12012,12 @@ S: Maintained
F: Documentation/devicetree/bindings/i2c/i2c-mt7621.txt
F: drivers/i2c/busses/i2c-mt7621.c
MEDIATEK MT7621 PCIE CONTROLLER DRIVER
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
S: Maintained
F: Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
F: drivers/pci/controller/pcie-mt7621.c
MEDIATEK MT7621 PHY PCI DRIVER
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
S: Maintained
......@@ -14647,9 +14660,12 @@ M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
R: Krzysztof Wilczyński <kw@linux.com>
L: linux-pci@vger.kernel.org
S: Supported
Q: https://patchwork.kernel.org/project/linux-pci/list/
B: https://bugzilla.kernel.org
C: irc://irc.oftc.net/linux-pci
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git
F: Documentation/PCI/endpoint/*
F: Documentation/misc-devices/pci-endpoint-test.rst
T: git git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git
F: drivers/misc/pci_endpoint_test.c
F: drivers/pci/endpoint/
F: tools/pci/
......@@ -14695,15 +14711,21 @@ R: Rob Herring <robh@kernel.org>
R: Krzysztof Wilczyński <kw@linux.com>
L: linux-pci@vger.kernel.org
S: Supported
Q: http://patchwork.ozlabs.org/project/linux-pci/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git/
Q: https://patchwork.kernel.org/project/linux-pci/list/
B: https://bugzilla.kernel.org
C: irc://irc.oftc.net/linux-pci
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git
F: drivers/pci/controller/
F: drivers/pci/pci-bridge-emul.c
F: drivers/pci/pci-bridge-emul.h
PCI SUBSYSTEM
M: Bjorn Helgaas <bhelgaas@google.com>
L: linux-pci@vger.kernel.org
S: Supported
Q: http://patchwork.ozlabs.org/project/linux-pci/list/
Q: https://patchwork.kernel.org/project/linux-pci/list/
B: https://bugzilla.kernel.org
C: irc://irc.oftc.net/linux-pci
T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
F: Documentation/PCI/
F: Documentation/devicetree/bindings/pci/
......@@ -14803,7 +14825,15 @@ M: Stanimir Varbanov <svarbanov@mm-sol.com>
L: linux-pci@vger.kernel.org
L: linux-arm-msm@vger.kernel.org
S: Maintained
F: drivers/pci/controller/dwc/*qcom*
F: drivers/pci/controller/dwc/pcie-qcom.c
PCIE ENDPOINT DRIVER FOR QUALCOMM
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-pci@vger.kernel.org
L: linux-arm-msm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
F: drivers/pci/controller/dwc/pcie-qcom-ep.c
PCIE DRIVER FOR ROCKCHIP
M: Shawn Lin <shawn.lin@rock-chips.com>
......
arch/microblaze/pci/pci-common.c
View file @ 0c5c62dd
......@@ -587,13 +587,12 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
int pcibios_add_device(struct pci_dev *dev)
int pcibios_device_add(struct pci_dev *dev)
{
dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
return 0;
}
EXPORT_SYMBOL(pcibios_add_device);
/*
* Reparent resource children of pr that conflict with res
......
arch/mips/ralink/Kconfig
View file @ 0c5c62dd
......@@ -51,7 +51,8 @@ choice
select SYS_SUPPORTS_HIGHMEM
select MIPS_GIC
select CLKSRC_MIPS_GIC
select HAVE_PCI if PCI_MT7621
select HAVE_PCI
select PCI_DRIVERS_GENERIC
select SOC_BUS
endchoice
......
arch/powerpc/include/asm/ppc-pci.h
View file @ 0c5c62dd
......@@ -55,11 +55,6 @@ void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode);
void eeh_sysfs_add_device(struct pci_dev *pdev);
void eeh_sysfs_remove_device(struct pci_dev *pdev);
static inline const char *eeh_driver_name(struct pci_dev *pdev)
{
return (pdev && pdev->driver) ? pdev->driver->name : "<null>";
}
#endif /* CONFIG_EEH */
#define PCI_BUSNO(bdfn) ((bdfn >> 8) & 0xff)
......
arch/powerpc/kernel/eeh.c
View file @ 0c5c62dd
......@@ -399,6 +399,14 @@ static int eeh_phb_check_failure(struct eeh_pe *pe)
return ret;
}
static inline const char *eeh_driver_name(struct pci_dev *pdev)
{
if (pdev)
return dev_driver_string(&pdev->dev);
return "<null>";
}
/**
* eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
* @edev: eeh device
......
arch/powerpc/kernel/eeh_driver.c
View file @ 0c5c62dd
......@@ -104,13 +104,13 @@ static bool eeh_edev_actionable(struct eeh_dev *edev)
*/
static inline struct pci_driver *eeh_pcid_get(struct pci_dev *pdev)
{
if (!pdev || !pdev->driver)
if (!pdev || !pdev->dev.driver)
return NULL;
if (!try_module_get(pdev->driver->driver.owner))
if (!try_module_get(pdev->dev.driver->owner))
return NULL;
return pdev->driver;
return to_pci_driver(pdev->dev.driver);
}
/**
......@@ -122,10 +122,10 @@ static inline struct pci_driver *eeh_pcid_get(struct pci_dev *pdev)
*/
static inline void eeh_pcid_put(struct pci_dev *pdev)
{
if (!pdev || !pdev->driver)
if (!pdev || !pdev->dev.driver)
return;
module_put(pdev->driver->driver.owner);
module_put(pdev->dev.driver->owner);
}
/**
......
arch/powerpc/kernel/pci-common.c
View file @ 0c5c62dd
......@@ -1059,7 +1059,7 @@ void pcibios_bus_add_device(struct pci_dev *dev)
ppc_md.pcibios_bus_add_device(dev);
}
int pcibios_add_device(struct pci_dev *dev)
int pcibios_device_add(struct pci_dev *dev)
{
struct irq_domain *d;
......
arch/powerpc/platforms/powernv/pci-sriov.c
View file @ 0c5c62dd
......@@ -51,7 +51,7 @@
* to "new_size", calculated above. Implementing this is a convoluted process
* which requires several hooks in the PCI core:
*
* 1. In pcibios_add_device() we call pnv_pci_ioda_fixup_iov().
* 1. In pcibios_device_add() we call pnv_pci_ioda_fixup_iov().
*
* At this point the device has been probed and the device's BARs are sized,
* but no resource allocations have been done. The SR-IOV BARs are sized
......
arch/s390/pci/pci.c
View file @ 0c5c62dd
......@@ -561,7 +561,7 @@ static void zpci_cleanup_bus_resources(struct zpci_dev *zdev)
zdev->has_resources = 0;
}
int pcibios_add_device(struct pci_dev *pdev)
int pcibios_device_add(struct pci_dev *pdev)
{
struct zpci_dev *zdev = to_zpci(pdev);
struct resource *res;
......
arch/sparc/kernel/pci.c
View file @ 0c5c62dd
......@@ -1010,7 +1010,7 @@ void pcibios_set_master(struct pci_dev *dev)
}
#ifdef CONFIG_PCI_IOV
int pcibios_add_device(struct pci_dev *dev)
int pcibios_device_add(struct pci_dev *dev)
{
struct pci_dev *pdev;
......
arch/x86/events/intel/uncore.c
View file @ 0c5c62dd
......@@ -1187,7 +1187,7 @@ static int uncore_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id
* PCI slot and func to indicate the uncore box.
*/
if (id->driver_data & ~0xffff) {
struct pci_driver *pci_drv = pdev->driver;
struct pci_driver *pci_drv = to_pci_driver(pdev->dev.driver);
pmu = uncore_pci_find_dev_pmu(pdev, pci_drv->id_table);
if (pmu == NULL)
......
arch/x86/kernel/probe_roms.c
View file @ 0c5c62dd
......@@ -80,7 +80,7 @@ static struct resource video_rom_resource = {
*/
static bool match_id(struct pci_dev *pdev, unsigned short vendor, unsigned short device)
{
struct pci_driver *drv = pdev->driver;
struct pci_driver *drv = to_pci_driver(pdev->dev.driver);
const struct pci_device_id *id;
if (pdev->vendor == vendor && pdev->device == device)
......
arch/x86/pci/common.c
View file @ 0c5c62dd
......@@ -632,7 +632,7 @@ static void set_dev_domain_options(struct pci_dev *pdev)
pdev->hotplug_user_indicators = 1;
}
int pcibios_add_device(struct pci_dev *dev)
int pcibios_device_add(struct pci_dev *dev)
{
struct pci_setup_rom *rom;
struct irq_domain *msidom;
......
drivers/acpi/pci_root.c
View file @ 0c5c62dd
......@@ -199,33 +199,20 @@ static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root,
acpi_status status;
u32 result, capbuf[3];
support &= OSC_PCI_SUPPORT_MASKS;
support |= root->osc_support_set;
capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
capbuf[OSC_SUPPORT_DWORD] = support;
if (control) {
*control &= OSC_PCI_CONTROL_MASKS;
capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
} else {
/* Run _OSC query only with existing controls. */
capbuf[OSC_CONTROL_DWORD] = root->osc_control_set;
}
capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
status = acpi_pci_run_osc(root->device->handle, capbuf, &result);
if (ACPI_SUCCESS(status)) {
root->osc_support_set = support;
if (control)
*control = result;
*control = result;
}
return status;
}
static acpi_status acpi_pci_osc_support(struct acpi_pci_root *root, u32 flags)
{
return acpi_pci_query_osc(root, flags, NULL);
}
struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
{
struct acpi_pci_root *root;
......@@ -348,8 +335,9 @@ EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
* _OSC bits the BIOS has granted control of, but its contents are meaningless
* on failure.
**/
static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 req)
static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 support)
{
u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
struct acpi_pci_root *root;
acpi_status status;
u32 ctrl, capbuf[3];
......@@ -357,22 +345,16 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 r
if (!mask)
return AE_BAD_PARAMETER;
ctrl = *mask & OSC_PCI_CONTROL_MASKS;
if ((ctrl & req) != req)
return AE_TYPE;
root = acpi_pci_find_root(handle);
if (!root)
return AE_NOT_EXIST;
*mask = ctrl | root->osc_control_set;
/* No need to evaluate _OSC if the control was already granted. */
if ((root->osc_control_set & ctrl) == ctrl)
return AE_OK;
ctrl = *mask;
*mask |= root->osc_control_set;
/* Need to check the available controls bits before requesting them. */
while (*mask) {
status = acpi_pci_query_osc(root, root->osc_support_set, mask);
do {
status = acpi_pci_query_osc(root, support, mask);
if (ACPI_FAILURE(status))
return status;
if (ctrl == *mask)
......@@ -380,7 +362,11 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 r
decode_osc_control(root, "platform does not support",
ctrl & ~(*mask));
ctrl = *mask;
}
} while (*mask);
/* No need to request _OSC if the control was already granted. */
if ((root->osc_control_set & ctrl) == ctrl)
return AE_OK;
if ((ctrl & req) != req) {
decode_osc_control(root, "not requesting control; platform does not support",
......@@ -399,25 +385,9 @@ static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask, u32 r
return AE_OK;
}
static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
bool is_pcie)
static u32 calculate_support(void)
{
u32 support, control, requested;
acpi_status status;
struct acpi_device *device = root->device;
acpi_handle handle = device->handle;
/*
* Apple always return failure on _OSC calls when _OSI("Darwin") has
* been called successfully. We know the feature set supported by the
* platform, so avoid calling _OSC at all
*/
if (x86_apple_machine) {
root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
decode_osc_control(root, "OS assumes control of",
root->osc_control_set);
return;
}
u32 support;
/*
* All supported architectures that use ACPI have support for
......@@ -434,30 +404,12 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
if (IS_ENABLED(CONFIG_PCIE_EDR))
support |= OSC_PCI_EDR_SUPPORT;
decode_osc_support(root, "OS supports", support);
status = acpi_pci_osc_support(root, support);
if (ACPI_FAILURE(status)) {
*no_aspm = 1;
/* _OSC is optional for PCI host bridges */
if ((status == AE_NOT_FOUND) && !is_pcie)
return;
dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
acpi_format_exception(status));
return;
}
if (pcie_ports_disabled) {
dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
return;
}
return support;
}
if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
decode_osc_support(root, "not requesting OS control; OS requires",
ACPI_PCIE_REQ_SUPPORT);
return;
}
static u32 calculate_control(void)
{
u32 control;
control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL
| OSC_PCI_EXPRESS_PME_CONTROL;
......@@ -483,11 +435,59 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
control |= OSC_PCI_EXPRESS_DPC_CONTROL;
requested = control;
status = acpi_pci_osc_control_set(handle, &control,
OSC_PCI_EXPRESS_CAPABILITY_CONTROL);
return control;
}
static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
{
struct acpi_device *device = root->device;
if (pcie_ports_disabled) {
dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
return false;
}
if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
decode_osc_support(root, "not requesting OS control; OS requires",
ACPI_PCIE_REQ_SUPPORT);
return false;
}
return true;
}
static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
bool is_pcie)
{
u32 support, control = 0, requested = 0;
acpi_status status;
struct acpi_device *device = root->device;
acpi_handle handle = device->handle;
/*
* Apple always return failure on _OSC calls when _OSI("Darwin") has
* been called successfully. We know the feature set supported by the
* platform, so avoid calling _OSC at all
*/
if (x86_apple_machine) {
root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
decode_osc_control(root, "OS assumes control of",
root->osc_control_set);
return;
}
support = calculate_support();
decode_osc_support(root, "OS supports", support);
if (os_control_query_checks(root, support))
requested = control = calculate_control();
status = acpi_pci_osc_control_set(handle, &control, support);
if (ACPI_SUCCESS(status)) {
decode_osc_control(root, "OS now controls", control);
if (control)
decode_osc_control(root, "OS now controls", control);
if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
/*
* We have ASPM control, but the FADT indicates that
......@@ -498,11 +498,6 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
*no_aspm = 1;
}
} else {
decode_osc_control(root, "OS requested", requested);
decode_osc_control(root, "platform willing to grant", control);
dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
acpi_format_exception(status));
/*
* We want to disable ASPM here, but aspm_disabled
* needs to remain in its state from boot so that we
......@@ -511,6 +506,18 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm,
* root scan.
*/
*no_aspm = 1;
/* _OSC is optional for PCI host bridges */
if ((status == AE_NOT_FOUND) && !is_pcie)
return;
if (control) {
decode_osc_control(root, "OS requested", requested);
decode_osc_control(root, "platform willing to grant", control);
}
dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
acpi_format_exception(status));
}
}
......
drivers/bcma/host_pci.c
View file @ 0c5c62dd
......@@ -162,7 +162,6 @@ static int bcma_host_pci_probe(struct pci_dev *dev,
{
struct bcma_bus *bus;
int err = -ENOMEM;
const char *name;
u32 val;
/* Alloc */
......@@ -175,10 +174,7 @@ static int bcma_host_pci_probe(struct pci_dev *dev,
if (err)
goto err_kfree_bus;
name = dev_name(&dev->dev);
if (dev->driver && dev->driver->name)
name = dev->driver->name;
err = pci_request_regions(dev, name);
err = pci_request_regions(dev, "bcma-pci-bridge");
if (err)
goto err_pci_disable;
pci_set_master(dev);
......
drivers/crypto/hisilicon/qm.c
View file @ 0c5c62dd
......@@ -3118,7 +3118,7 @@ static int qm_alloc_uacce(struct hisi_qm *qm)
};
int ret;
ret = strscpy(interface.name, pdev->driver->name,
ret = strscpy(interface.name, dev_driver_string(&pdev->dev),
sizeof(interface.name));
if (ret < 0)
return -ENAMETOOLONG;
......
drivers/crypto/qat/qat_4xxx/adf_drv.c
View file @ 0c5c62dd
......@@ -247,11 +247,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
pci_set_master(pdev);
if (adf_enable_aer(accel_dev)) {
dev_err(&pdev->dev, "Failed to enable aer.\n");
ret = -EFAULT;
goto out_err;
}
adf_enable_aer(accel_dev);
if (pci_save_state(pdev)) {
dev_err(&pdev->dev, "Failed to save pci state.\n");
......@@ -304,6 +300,7 @@ static struct pci_driver adf_driver = {
.probe = adf_probe,
.remove = adf_remove,
.sriov_configure = adf_sriov_configure,
.err_handler = &adf_err_handler,
};
module_pci_driver(adf_driver);
......
drivers/crypto/qat/qat_c3xxx/adf_drv.c
View file @ 0c5c62dd
......@@ -33,6 +33,7 @@ static struct pci_driver adf_driver = {
.probe = adf_probe,
.remove = adf_remove,
.sriov_configure = adf_sriov_configure,
.err_handler = &adf_err_handler,
};
static void adf_cleanup_pci_dev(struct adf_accel_dev *accel_dev)
......@@ -192,11 +193,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
pci_set_master(pdev);
if (adf_enable_aer(accel_dev)) {
dev_err(&pdev->dev, "Failed to enable aer\n");
ret = -EFAULT;
goto out_err_free_reg;
}
adf_enable_aer(accel_dev);
if (pci_save_state(pdev)) {
dev_err(&pdev->dev, "Failed to save pci state\n");
......
drivers/crypto/qat/qat_c62x/adf_drv.c
View file @ 0c5c62dd
......@@ -33,6 +33,7 @@ static struct pci_driver adf_driver = {
.probe = adf_probe,
.remove = adf_remove,
.sriov_configure = adf_sriov_configure,
.err_handler = &adf_err_handler,
};
static void adf_cleanup_pci_dev(struct adf_accel_dev *accel_dev)
......@@ -192,11 +193,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
pci_set_master(pdev);
if (adf_enable_aer(accel_dev)) {
dev_err(&pdev->dev, "Failed to enable aer\n");
ret = -EFAULT;
goto out_err_free_reg;
}
adf_enable_aer(accel_dev);
if (pci_save_state(pdev)) {
dev_err(&pdev->dev, "Failed to save pci state\n");
......
drivers/crypto/qat/qat_common/adf_aer.c
View file @ 0c5c62dd
......@@ -166,11 +166,12 @@ static void adf_resume(struct pci_dev *pdev)
dev_info(&pdev->dev, "Device is up and running\n");
}
static const struct pci_error_handlers adf_err_handler = {
const struct pci_error_handlers adf_err_handler = {
.error_detected = adf_error_detected,
.slot_reset = adf_slot_reset,
.resume = adf_resume,
};
EXPORT_SYMBOL_GPL(adf_err_handler);
/**
* adf_enable_aer() - Enable Advance Error Reporting for acceleration device
......@@ -179,17 +180,12 @@ static const struct pci_error_handlers adf_err_handler = {
* Function enables PCI Advance Error Reporting for the
* QAT acceleration device accel_dev.
* To be used by QAT device specific drivers.
*
* Return: 0 on success, error code otherwise.
*/
int adf_enable_aer(struct adf_accel_dev *accel_dev)
void adf_enable_aer(struct adf_accel_dev *accel_dev)
{
struct pci_dev *pdev = accel_to_pci_dev(accel_dev);
struct pci_driver *pdrv = pdev->driver;
pdrv->err_handler = &adf_err_handler;
pci_enable_pcie_error_reporting(pdev);
return 0;
}
EXPORT_SYMBOL_GPL(adf_enable_aer);
......
drivers/crypto/qat/qat_common/adf_common_drv.h
View file @ 0c5c62dd
......@@ -94,7 +94,8 @@ void adf_ae_fw_release(struct adf_accel_dev *accel_dev);
int adf_ae_start(struct adf_accel_dev *accel_dev);
int adf_ae_stop(struct adf_accel_dev *accel_dev);
int adf_enable_aer(struct adf_accel_dev *accel_dev);
extern const struct pci_error_handlers adf_err_handler;
void adf_enable_aer(struct adf_accel_dev *accel_dev);
void adf_disable_aer(struct adf_accel_dev *accel_dev);
void adf_reset_sbr(struct adf_accel_dev *accel_dev);
void adf_reset_flr(struct adf_accel_dev *accel_dev);
......
drivers/crypto/qat/qat_dh895xcc/adf_drv.c
View file @ 0c5c62dd
......@@ -33,6 +33,7 @@ static struct pci_driver adf_driver = {
.probe = adf_probe,
.remove = adf_remove,
.sriov_configure = adf_sriov_configure,
.err_handler = &adf_err_handler,
};
static void adf_cleanup_pci_dev(struct adf_accel_dev *accel_dev)
......@@ -192,11 +193,7 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
pci_set_master(pdev);
if (adf_enable_aer(accel_dev)) {
dev_err(&pdev->dev, "Failed to enable aer\n");
ret = -EFAULT;
goto out_err_free_reg;
}
adf_enable_aer(accel_dev);
if (pci_save_state(pdev)) {
dev_err(&pdev->dev, "Failed to save pci state\n");
......
drivers/iommu/apple-dart.c
View file @ 0c5c62dd
......@@ -15,6 +15,7 @@
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/dev_printk.h>
#include <linux/dma-iommu.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
......@@ -737,6 +738,31 @@ static int apple_dart_def_domain_type(struct device *dev)
return 0;
}
#ifndef CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR
/* Keep things compiling when CONFIG_PCI_APPLE isn't selected */
#define CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR 0
#endif
#define DOORBELL_ADDR (CONFIG_PCIE_APPLE_MSI_DOORBELL_ADDR & PAGE_MASK)
static void apple_dart_get_resv_regions(struct device *dev,
struct list_head *head)
{
if (IS_ENABLED(CONFIG_PCIE_APPLE) && dev_is_pci(dev)) {
struct iommu_resv_region *region;
int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
region = iommu_alloc_resv_region(DOORBELL_ADDR,
PAGE_SIZE, prot,
IOMMU_RESV_MSI);
if (!region)
return;
list_add_tail(&region->list, head);
}
iommu_dma_get_resv_regions(dev, head);
}
static const struct iommu_ops apple_dart_iommu_ops = {
.domain_alloc = apple_dart_domain_alloc,
.domain_free = apple_dart_domain_free,
......@@ -753,6 +779,8 @@ static const struct iommu_ops apple_dart_iommu_ops = {
.device_group = apple_dart_device_group,
.of_xlate = apple_dart_of_xlate,
.def_domain_type = apple_dart_def_domain_type,
.get_resv_regions = apple_dart_get_resv_regions,
.put_resv_regions = generic_iommu_put_resv_regions,
.pgsize_bitmap = -1UL, /* Restricted during dart probe */
};
......
drivers/message/fusion/mptbase.c
View file @ 0c5c62dd
......@@ -829,7 +829,6 @@ int
mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
{
MPT_ADAPTER *ioc;
const struct pci_device_id *id;
if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
return -EINVAL;
......@@ -838,10 +837,8 @@ mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
/* call per pci device probe entry point */
list_for_each_entry(ioc, &ioc_list, list) {
id = ioc->pcidev->driver ?
ioc->pcidev->driver->id_table : NULL;
if (dd_cbfunc->probe)
dd_cbfunc->probe(ioc->pcidev, id);
dd_cbfunc->probe(ioc->pcidev);
}
return 0;
......@@ -2032,7 +2029,7 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
if(MptDeviceDriverHandlers[cb_idx] &&
MptDeviceDriverHandlers[cb_idx]->probe) {
MptDeviceDriverHandlers[cb_idx]->probe(pdev,id);
MptDeviceDriverHandlers[cb_idx]->probe(pdev);
}
}
......
drivers/message/fusion/mptbase.h
View file @ 0c5c62dd
......@@ -257,7 +257,7 @@ typedef enum {
} MPT_DRIVER_CLASS;
struct mpt_pci_driver{
int (*probe) (struct pci_dev *dev, const struct pci_device_id *id);
int (*probe) (struct pci_dev *dev);
void (*remove) (struct pci_dev *dev);
};
......
drivers/message/fusion/mptctl.c
View file @ 0c5c62dd
......@@ -114,7 +114,7 @@ static int mptctl_do_reset(MPT_ADAPTER *iocp, unsigned long arg);
static int mptctl_hp_hostinfo(MPT_ADAPTER *iocp, unsigned long arg, unsigned int cmd);
static int mptctl_hp_targetinfo(MPT_ADAPTER *iocp, unsigned long arg);
static int mptctl_probe(struct pci_dev *, const struct pci_device_id *);
static int mptctl_probe(struct pci_dev *);
static void mptctl_remove(struct pci_dev *);
#ifdef CONFIG_COMPAT
......@@ -2838,7 +2838,7 @@ static long compat_mpctl_ioctl(struct file *f, unsigned int cmd, unsigned long a
*/
static int
mptctl_probe(struct pci_dev *pdev, const struct pci_device_id *id)
mptctl_probe(struct pci_dev *pdev)
{
MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
......
drivers/message/fusion/mptlan.c
View file @ 0c5c62dd
......@@ -1377,7 +1377,7 @@ mpt_register_lan_device (MPT_ADAPTER *mpt_dev, int pnum)
}
static int
mptlan_probe(struct pci_dev *pdev, const struct pci_device_id *id)
mptlan_probe(struct pci_dev *pdev)
{
MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
struct net_device *dev;
......
drivers/misc/cxl/guest.c
View file @ 0c5c62dd
......@@ -20,34 +20,38 @@ static void pci_error_handlers(struct cxl_afu *afu,
pci_channel_state_t state)
{
struct pci_dev *afu_dev;
struct pci_driver *afu_drv;
const struct pci_error_handlers *err_handler;
if (afu->phb == NULL)
return;
list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
if (!afu_dev->driver)
afu_drv = to_pci_driver(afu_dev->dev.driver);
if (!afu_drv)
continue;
err_handler = afu_drv->err_handler;
switch (bus_error_event) {
case CXL_ERROR_DETECTED_EVENT:
afu_dev->error_state = state;
if (afu_dev->driver->err_handler &&
afu_dev->driver->err_handler->error_detected)
afu_dev->driver->err_handler->error_detected(afu_dev, state);
break;
if (err_handler &&
err_handler->error_detected)
err_handler->error_detected(afu_dev, state);
break;
case CXL_SLOT_RESET_EVENT:
afu_dev->error_state = state;
if (afu_dev->driver->err_handler &&
afu_dev->driver->err_handler->slot_reset)
afu_dev->driver->err_handler->slot_reset(afu_dev);
break;
if (err_handler &&
err_handler->slot_reset)
err_handler->slot_reset(afu_dev);
break;
case CXL_RESUME_EVENT:
if (afu_dev->driver->err_handler &&
afu_dev->driver->err_handler->resume)
afu_dev->driver->err_handler->resume(afu_dev);
break;
if (err_handler &&
err_handler->resume)
err_handler->resume(afu_dev);
break;
}
}
}
......
drivers/misc/cxl/pci.c
View file @ 0c5c62dd
......@@ -1795,6 +1795,8 @@ static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
pci_channel_state_t state)
{
struct pci_dev *afu_dev;
struct pci_driver *afu_drv;
const struct pci_error_handlers *err_handler;
pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
......@@ -1805,14 +1807,16 @@ static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
return result;
list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
if (!afu_dev->driver)
afu_drv = to_pci_driver(afu_dev->dev.driver);
if (!afu_drv)
continue;
afu_dev->error_state = state;
if (afu_dev->driver->err_handler)
afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
state);
err_handler = afu_drv->err_handler;
if (err_handler)
afu_result = err_handler->error_detected(afu_dev,
state);
/* Disconnect trumps all, NONE trumps NEED_RESET */
if (afu_result == PCI_ERS_RESULT_DISCONNECT)
result = PCI_ERS_RESULT_DISCONNECT;
......@@ -1972,6 +1976,8 @@ static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
struct cxl_afu *afu;
struct cxl_context *ctx;
struct pci_dev *afu_dev;
struct pci_driver *afu_drv;
const struct pci_error_handlers *err_handler;
pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
int i;
......@@ -2028,12 +2034,13 @@ static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
* shouldn't start new work until we call
* their resume function.
*/
if (!afu_dev->driver)
afu_drv = to_pci_driver(afu_dev->dev.driver);
if (!afu_drv)
continue;
if (afu_dev->driver->err_handler &&
afu_dev->driver->err_handler->slot_reset)
afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
err_handler = afu_drv->err_handler;
if (err_handler && err_handler->slot_reset)
afu_result = err_handler->slot_reset(afu_dev);
if (afu_result == PCI_ERS_RESULT_DISCONNECT)
result = PCI_ERS_RESULT_DISCONNECT;
......@@ -2060,6 +2067,8 @@ static void cxl_pci_resume(struct pci_dev *pdev)
struct cxl *adapter = pci_get_drvdata(pdev);
struct cxl_afu *afu;
struct pci_dev *afu_dev;
struct pci_driver *afu_drv;
const struct pci_error_handlers *err_handler;
int i;
/* Everything is back now. Drivers should restart work now.
......@@ -2074,9 +2083,13 @@ static void cxl_pci_resume(struct pci_dev *pdev)
continue;
list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
if (afu_dev->driver && afu_dev->driver->err_handler &&
afu_dev->driver->err_handler->resume)
afu_dev->driver->err_handler->resume(afu_dev);
afu_drv = to_pci_driver(afu_dev->dev.driver);
if (!afu_drv)
continue;
err_handler = afu_drv->err_handler;
if (err_handler && err_handler->resume)
err_handler->resume(afu_dev);
}
}
spin_unlock(&adapter->afu_list_lock);
......
drivers/net/ethernet/chelsio/cxgb3/common.h
View file @ 0c5c62dd
......@@ -676,8 +676,6 @@ void t3_link_changed(struct adapter *adapter, int port_id);
void t3_link_fault(struct adapter *adapter, int port_id);
int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data);
int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data);
int t3_seeprom_wp(struct adapter *adapter, int enable);
int t3_get_tp_version(struct adapter *adapter, u32 *vers);
int t3_check_tpsram_version(struct adapter *adapter);
......
drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c
View file @ 0c5c62dd
......@@ -2036,20 +2036,16 @@ static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
{
struct port_info *pi = netdev_priv(dev);
struct adapter *adapter = pi->adapter;
int i, err = 0;
u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
if (!buf)
return -ENOMEM;
int cnt;
e->magic = EEPROM_MAGIC;
for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
err = t3_seeprom_read(adapter, i, (__le32 *) & buf[i]);
cnt = pci_read_vpd(adapter->pdev, e->offset, e->len, data);
if (cnt < 0)
return cnt;
if (!err)
memcpy(data, buf + e->offset, e->len);
kfree(buf);
return err;
e->len = cnt;
return 0;
}
static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
......@@ -2058,7 +2054,6 @@ static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
struct port_info *pi = netdev_priv(dev);
struct adapter *adapter = pi->adapter;
u32 aligned_offset, aligned_len;
__le32 *p;
u8 *buf;
int err;
......@@ -2072,12 +2067,9 @@ static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
buf = kmalloc(aligned_len, GFP_KERNEL);
if (!buf)
return -ENOMEM;
err = t3_seeprom_read(adapter, aligned_offset, (__le32 *) buf);
if (!err && aligned_len > 4)
err = t3_seeprom_read(adapter,
aligned_offset + aligned_len - 4,
(__le32 *) & buf[aligned_len - 4]);
if (err)
err = pci_read_vpd(adapter->pdev, aligned_offset, aligned_len,
buf);
if (err < 0)
goto out;
memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
} else
......@@ -2087,17 +2079,13 @@ static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
if (err)
goto out;
for (p = (__le32 *) buf; !err && aligned_len; aligned_len -= 4, p++) {
err = t3_seeprom_write(adapter, aligned_offset, *p);
aligned_offset += 4;
}
if (!err)
err = pci_write_vpd(adapter->pdev, aligned_offset, aligned_len, buf);
if (err >= 0)
err = t3_seeprom_wp(adapter, 1);
out:
if (buf != data)
kfree(buf);
return err;
return err < 0 ? err : 0;
}
static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
......
drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
View file @ 0c5c62dd
......@@ -596,80 +596,9 @@ struct t3_vpd {
u32 pad; /* for multiple-of-4 sizing and alignment */
};
#define EEPROM_MAX_POLL 40
#define EEPROM_STAT_ADDR 0x4000
#define VPD_BASE 0xc00
/**
* t3_seeprom_read - read a VPD EEPROM location
* @adapter: adapter to read
* @addr: EEPROM address
* @data: where to store the read data
*
* Read a 32-bit word from a location in VPD EEPROM using the card's PCI
* VPD ROM capability. A zero is written to the flag bit when the
* address is written to the control register. The hardware device will
* set the flag to 1 when 4 bytes have been read into the data register.
*/
int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data)
{
u16 val;
int attempts = EEPROM_MAX_POLL;
u32 v;
unsigned int base = adapter->params.pci.vpd_cap_addr;
if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
return -EINVAL;
pci_write_config_word(adapter->pdev, base + PCI_VPD_ADDR, addr);
do {
udelay(10);
pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val);
} while (!(val & PCI_VPD_ADDR_F) && --attempts);
if (!(val & PCI_VPD_ADDR_F)) {
CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr);
return -EIO;
}
pci_read_config_dword(adapter->pdev, base + PCI_VPD_DATA, &v);
*data = cpu_to_le32(v);
return 0;
}
/**
* t3_seeprom_write - write a VPD EEPROM location
* @adapter: adapter to write
* @addr: EEPROM address
* @data: value to write
*
* Write a 32-bit word to a location in VPD EEPROM using the card's PCI
* VPD ROM capability.
*/
int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data)
{
u16 val;
int attempts = EEPROM_MAX_POLL;
unsigned int base = adapter->params.pci.vpd_cap_addr;
if ((addr >= EEPROMSIZE && addr != EEPROM_STAT_ADDR) || (addr & 3))
return -EINVAL;
pci_write_config_dword(adapter->pdev, base + PCI_VPD_DATA,
le32_to_cpu(data));
pci_write_config_word(adapter->pdev,base + PCI_VPD_ADDR,
addr | PCI_VPD_ADDR_F);
do {
msleep(1);
pci_read_config_word(adapter->pdev, base + PCI_VPD_ADDR, &val);
} while ((val & PCI_VPD_ADDR_F) && --attempts);
if (val & PCI_VPD_ADDR_F) {
CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr);
return -EIO;
}
return 0;
}
/**
* t3_seeprom_wp - enable/disable EEPROM write protection
* @adapter: the adapter
......@@ -679,7 +608,14 @@ int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data)
*/
int t3_seeprom_wp(struct adapter *adapter, int enable)
{
return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
u32 data = enable ? 0xc : 0;
int ret;
/* EEPROM_STAT_ADDR is outside VPD area, use pci_write_vpd_any() */
ret = pci_write_vpd_any(adapter->pdev, EEPROM_STAT_ADDR, sizeof(u32),
&data);
return ret < 0 ? ret : 0;
}
static int vpdstrtouint(char *s, u8 len, unsigned int base, unsigned int *val)
......@@ -709,24 +645,22 @@ static int vpdstrtou16(char *s, u8 len, unsigned int base, u16 *val)
*/
static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
{
int i, addr, ret;
struct t3_vpd vpd;
u8 base_val = 0;
int addr, ret;
/*
* Card information is normally at VPD_BASE but some early cards had
* it at 0.
*/
ret = t3_seeprom_read(adapter, VPD_BASE, (__le32 *)&vpd);
if (ret)
ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val);
if (ret < 0)
return ret;
addr = vpd.id_tag == 0x82 ? VPD_BASE : 0;
addr = base_val == PCI_VPD_LRDT_ID_STRING ? VPD_BASE : 0;
for (i = 0; i < sizeof(vpd); i += 4) {
ret = t3_seeprom_read(adapter, addr + i,
(__le32 *)((u8 *)&vpd + i));
if (ret)
return ret;
}
ret = pci_read_vpd(adapter->pdev, addr, sizeof(vpd), &vpd);
if (ret < 0)
return ret;
ret = vpdstrtouint(vpd.cclk_data, vpd.cclk_len, 10, &p->cclk);
if (ret)
......
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
View file @ 0c5c62dd
......@@ -608,7 +608,7 @@ static void hns3_get_drvinfo(struct net_device *netdev,
return;
}
strncpy(drvinfo->driver, h->pdev->driver->name,
strncpy(drvinfo->driver, dev_driver_string(&h->pdev->dev),
sizeof(drvinfo->driver));
drvinfo->driver[sizeof(drvinfo->driver) - 1] = '\0';
......
drivers/net/ethernet/marvell/prestera/prestera_pci.c
View file @ 0c5c62dd
......@@ -776,7 +776,7 @@ static int prestera_fw_load(struct prestera_fw *fw)
static int prestera_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
const char *driver_name = pdev->driver->name;
const char *driver_name = dev_driver_string(&pdev->dev);
struct prestera_fw *fw;
int err;
......
drivers/net/ethernet/mellanox/mlxsw/pci.c
View file @ 0c5c62dd
......@@ -1875,7 +1875,7 @@ static void mlxsw_pci_cmd_fini(struct mlxsw_pci *mlxsw_pci)
static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
const char *driver_name = pdev->driver->name;
const char *driver_name = dev_driver_string(&pdev->dev);
struct mlxsw_pci *mlxsw_pci;
int err;
......
drivers/net/ethernet/netronome/nfp/nfp_net_ethtool.c
View file @ 0c5c62dd
......@@ -202,7 +202,8 @@ nfp_get_drvinfo(struct nfp_app *app, struct pci_dev *pdev,
{
char nsp_version[ETHTOOL_FWVERS_LEN] = {};
strlcpy(drvinfo->driver, pdev->driver->name, sizeof(drvinfo->driver));
strlcpy(drvinfo->driver, dev_driver_string(&pdev->dev),
sizeof(drvinfo->driver));
nfp_net_get_nspinfo(app, nsp_version);
snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
"%s %s %s %s", vnic_version, nsp_version,
......
drivers/of/irq.c
View file @ 0c5c62dd
......@@ -156,10 +156,14 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
/* Now start the actual "proper" walk of the interrupt tree */
while (ipar != NULL) {
/* Now check if cursor is an interrupt-controller and if it is
* then we are done
/*
* Now check if cursor is an interrupt-controller and
* if it is then we are done, unless there is an
* interrupt-map which takes precedence.
*/
if (of_property_read_bool(ipar, "interrupt-controller")) {
imap = of_get_property(ipar, "interrupt-map", &imaplen);
if (imap == NULL &&
of_property_read_bool(ipar, "interrupt-controller")) {
pr_debug(" -> got it !\n");
return 0;
}
......@@ -173,8 +177,6 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
goto fail;
}
/* Now look for an interrupt-map */
imap = of_get_property(ipar, "interrupt-map", &imaplen);
/* No interrupt map, check for an interrupt parent */
if (imap == NULL) {
pr_debug(" -> no map, getting parent\n");
......@@ -255,6 +257,11 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
out_irq->args_count = intsize = newintsize;
addrsize = newaddrsize;
if (ipar == newpar) {
pr_debug("%pOF interrupt-map entry to self\n", ipar);
return 0;
}
skiplevel:
/* Iterate again with new parent */
out_irq->np = newpar;
......
drivers/pci/controller/Kconfig
View file @ 0c5c62dd
......@@ -254,7 +254,7 @@ config PCIE_MEDIATEK_GEN3
MediaTek SoCs.
config VMD
depends on PCI_MSI && X86_64 && SRCU
depends on PCI_MSI && X86_64 && SRCU && !UML
tristate "Intel Volume Management Device Driver"
help
Adds support for the Intel Volume Management Device (VMD). VMD is a
......@@ -312,6 +312,32 @@ config PCIE_HISI_ERR
Say Y here if you want error handling support
for the PCIe controller's errors on HiSilicon HIP SoCs
config PCIE_APPLE_MSI_DOORBELL_ADDR
hex
default 0xfffff000
depends on PCIE_APPLE
config PCIE_APPLE
tristate "Apple PCIe controller"
depends on ARCH_APPLE || COMPILE_TEST
depends on OF
depends on PCI_MSI_IRQ_DOMAIN
select PCI_HOST_COMMON
help
Say Y here if you want to enable PCIe controller support on Apple
system-on-chips, like the Apple M1. This is required for the USB
type-A ports, Ethernet, Wi-Fi, and Bluetooth.
If unsure, say Y if you have an Apple Silicon system.
config PCIE_MT7621
tristate "MediaTek MT7621 PCIe Controller"
depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
select PHY_MT7621_PCI
default SOC_MT7621
help
This selects a driver for the MediaTek MT7621 PCIe Controller.
source "drivers/pci/controller/dwc/Kconfig"
source "drivers/pci/controller/mobiveil/Kconfig"
source "drivers/pci/controller/cadence/Kconfig"
......
drivers/pci/controller/Makefile
View file @ 0c5c62dd
......@@ -37,6 +37,9 @@ obj-$(CONFIG_VMD) += vmd.o
obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
obj-y += dwc/
obj-y += mobiveil/
......
drivers/pci/controller/cadence/pci-j721e.c
View file @ 0c5c62dd
......@@ -474,7 +474,7 @@ static int j721e_pcie_probe(struct platform_device *pdev)
ret = clk_prepare_enable(clk);
if (ret) {
dev_err(dev, "failed to enable pcie_refclk\n");
goto err_get_sync;
goto err_pcie_setup;
}
pcie->refclk = clk;
......
drivers/pci/controller/cadence/pcie-cadence-plat.c
View file @ 0c5c62dd
......@@ -127,6 +127,8 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
goto err_init;
}
return 0;
err_init:
err_get_sync:
pm_runtime_put_sync(dev);
......
drivers/pci/controller/dwc/Kconfig
View file @ 0c5c62dd
......@@ -8,22 +8,20 @@ config PCIE_DW
config PCIE_DW_HOST
bool
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW
config PCIE_DW_EP
bool
depends on PCI_ENDPOINT
select PCIE_DW
config PCI_DRA7XX
bool
tristate
config PCI_DRA7XX_HOST
bool "TI DRA7xx PCIe controller Host Mode"
tristate "TI DRA7xx PCIe controller Host Mode"
depends on SOC_DRA7XX || COMPILE_TEST
depends on PCI_MSI_IRQ_DOMAIN
depends on OF && HAS_IOMEM && TI_PIPE3
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
select PCI_DRA7XX
default y if SOC_DRA7XX
......@@ -36,10 +34,10 @@ config PCI_DRA7XX_HOST
This uses the DesignWare core.
config PCI_DRA7XX_EP
bool "TI DRA7xx PCIe controller Endpoint Mode"
tristate "TI DRA7xx PCIe controller Endpoint Mode"
depends on SOC_DRA7XX || COMPILE_TEST
depends on PCI_ENDPOINT
depends on OF && HAS_IOMEM && TI_PIPE3
depends on PCI_ENDPOINT
select PCIE_DW_EP
select PCI_DRA7XX
help
......@@ -55,7 +53,7 @@ config PCIE_DW_PLAT
config PCIE_DW_PLAT_HOST
bool "Platform bus based DesignWare PCIe Controller - Host mode"
depends on PCI && PCI_MSI_IRQ_DOMAIN
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
select PCIE_DW_PLAT
help
......@@ -138,8 +136,8 @@ config PCI_LAYERSCAPE
bool "Freescale Layerscape PCIe controller - Host mode"
depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
depends on PCI_MSI_IRQ_DOMAIN
select MFD_SYSCON
select PCIE_DW_HOST
select MFD_SYSCON
help
Say Y here if you want to enable PCIe controller support on Layerscape
SoCs to work in Host mode.
......@@ -180,6 +178,16 @@ config PCIE_QCOM
PCIe controller uses the DesignWare core plus Qualcomm-specific
hardware wrappers.
config PCIE_QCOM_EP
tristate "Qualcomm PCIe controller - Endpoint mode"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
depends on PCI_ENDPOINT
select PCIE_DW_EP
help
Say Y here to enable support for the PCIe controllers on Qualcomm SoCs
to work in endpoint mode. The PCIe controller uses the DesignWare core
plus Qualcomm-specific hardware wrappers.
config PCIE_ARMADA_8K
bool "Marvell Armada-8K PCIe controller"
depends on ARCH_MVEBU || COMPILE_TEST
......@@ -266,7 +274,7 @@ config PCIE_KEEMBAY_EP
config PCIE_KIRIN
depends on OF && (ARM64 || COMPILE_TEST)
bool "HiSilicon Kirin series SoCs PCIe controllers"
tristate "HiSilicon Kirin series SoCs PCIe controllers"
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
help
......@@ -283,8 +291,8 @@ config PCIE_HISI_STB
config PCI_MESON
tristate "MESON PCIe controller"
depends on PCI_MSI_IRQ_DOMAIN
default m if ARCH_MESON
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
help
Say Y here if you want to enable PCI controller support on Amlogic
......
drivers/pci/controller/dwc/Makefile
View file @ 0c5c62dd
......@@ -12,6 +12,7 @@ obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
obj-$(CONFIG_PCI_LAYERSCAPE_EP) += pci-layerscape-ep.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_ROCKCHIP_DW_HOST) += pcie-dw-rockchip.o
......
drivers/pci/controller/dwc/pci-dra7xx.c
View file @ 0c5c62dd
......@@ -7,6 +7,7 @@
* Authors: Kishon Vijay Abraham I <kishon@ti.com>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
......@@ -14,7 +15,7 @@
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_gpio.h>
#include <linux/of_pci.h>
......@@ -90,6 +91,7 @@ struct dra7xx_pcie {
int phy_count; /* DT phy-names count */
struct phy **phy;
struct irq_domain *irq_domain;
struct clk *clk;
enum dw_pcie_device_mode mode;
};
......@@ -607,6 +609,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
},
{},
};
MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match);
/*
* dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
......@@ -740,6 +743,15 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
if (!link)
return -ENOMEM;
dra7xx->clk = devm_clk_get_optional(dev, NULL);
if (IS_ERR(dra7xx->clk))
return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
"clock request failed");
ret = clk_prepare_enable(dra7xx->clk);
if (ret)
return ret;
for (i = 0; i < phy_count; i++) {
snprintf(name, sizeof(name), "pcie-phy%d", i);
phy[i] = devm_phy_get(dev, name);
......@@ -925,6 +937,8 @@ static void dra7xx_pcie_shutdown(struct platform_device *pdev)
pm_runtime_disable(dev);
dra7xx_pcie_disable_phy(dra7xx);
clk_disable_unprepare(dra7xx->clk);
}
static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
......@@ -943,4 +957,8 @@ static struct platform_driver dra7xx_pcie_driver = {
},
.shutdown = dra7xx_pcie_shutdown,
};
builtin_platform_driver(dra7xx_pcie_driver);
module_platform_driver(dra7xx_pcie_driver);
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs");
MODULE_LICENSE("GPL v2");
drivers/pci/controller/dwc/pci-imx6.c
View file @ 0c5c62dd
......@@ -1132,7 +1132,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
/* Limit link speed */
pci->link_gen = 1;
ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
if (IS_ERR(imx6_pcie->vpcie)) {
......
drivers/pci/controller/dwc/pcie-designware-ep.c
View file @ 0c5c62dd
......@@ -83,6 +83,7 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
for (func_no = 0; func_no < funcs; func_no++)
__dw_pcie_ep_reset_bar(pci, func_no, bar, 0);
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_reset_bar);
static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie_ep *ep, u8 func_no,
u8 cap_ptr, u8 cap)
......@@ -485,6 +486,7 @@ int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
return -EINVAL;
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_legacy_irq);
int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
u8 interrupt_num)
......@@ -536,6 +538,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_msi_irq);
int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
u16 interrupt_num)
......
drivers/pci/controller/dwc/pcie-designware-host.c
View file @ 0c5c62dd
......@@ -335,6 +335,16 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (pci->link_gen < 1)
pci->link_gen = of_pci_get_max_link_speed(np);
/* Set default bus ops */
bridge->ops = &dw_pcie_ops;
bridge->child_ops = &dw_child_pcie_ops;
if (pp->ops->host_init) {
ret = pp->ops->host_init(pp);
if (ret)
return ret;
}
if (pci_msi_enabled()) {
pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
of_property_read_bool(np, "msi-parent") ||
......@@ -388,15 +398,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
/* Set default bus ops */
bridge->ops = &dw_pcie_ops;
bridge->child_ops = &dw_child_pcie_ops;
if (pp->ops->host_init) {
ret = pp->ops->host_init(pp);
if (ret)
goto err_free_msi;
}
dw_pcie_iatu_detect(pci);
dw_pcie_setup_rc(pp);
......
drivers/pci/controller/dwc/pcie-designware.c
View file @ 0c5c62dd
......@@ -538,6 +538,7 @@ int dw_pcie_link_up(struct dw_pcie *pci)
return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
}
EXPORT_SYMBOL_GPL(dw_pcie_link_up);
void dw_pcie_upconfig_setup(struct dw_pcie *pci)
{
......
drivers/pci/controller/dwc/pcie-kirin.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/controller/dwc/pcie-qcom-ep.c 0 → 100644
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/controller/dwc/pcie-qcom.c
View file @ 0c5c62dd
......@@ -166,6 +166,9 @@ struct qcom_pcie_resources_2_7_0 {
struct regulator_bulk_data supplies[2];
struct reset_control *pci_reset;
struct clk *pipe_clk;
struct clk *pipe_clk_src;
struct clk *phy_pipe_clk;
struct clk *ref_clk_src;
};
union qcom_pcie_resources {
......@@ -189,6 +192,11 @@ struct qcom_pcie_ops {
int (*config_sid)(struct qcom_pcie *pcie);
};
struct qcom_pcie_cfg {
const struct qcom_pcie_ops *ops;
unsigned int pipe_clk_need_muxing:1;
};
struct qcom_pcie {
struct dw_pcie *pci;
void __iomem *parf; /* DT parf */
......@@ -197,6 +205,7 @@ struct qcom_pcie {
struct phy *phy;
struct gpio_desc *reset;
const struct qcom_pcie_ops *ops;
unsigned int pipe_clk_need_muxing:1;
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
......@@ -1167,6 +1176,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret < 0)
return ret;
if (pcie->pipe_clk_need_muxing) {
res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
if (IS_ERR(res->pipe_clk_src))
return PTR_ERR(res->pipe_clk_src);
res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe");
if (IS_ERR(res->phy_pipe_clk))
return PTR_ERR(res->phy_pipe_clk);
res->ref_clk_src = devm_clk_get(dev, "ref");
if (IS_ERR(res->ref_clk_src))
return PTR_ERR(res->ref_clk_src);
}
res->pipe_clk = devm_clk_get(dev, "pipe");
return PTR_ERR_OR_ZERO(res->pipe_clk);
}
......@@ -1185,6 +1208,10 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
return ret;
}
/* Set TCXO as clock source for pcie_pipe_clk_src */
if (pcie->pipe_clk_need_muxing)
clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
if (ret < 0)
goto err_disable_regulators;
......@@ -1256,6 +1283,10 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
/* Set pipe clock as clock source for pcie_pipe_clk_src */
if (pcie->pipe_clk_need_muxing)
clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
return clk_prepare_enable(res->pipe_clk);
}
......@@ -1456,6 +1487,39 @@ static const struct qcom_pcie_ops ops_1_9_0 = {
.config_sid = qcom_pcie_config_sid_sm8250,
};
static const struct qcom_pcie_cfg apq8084_cfg = {
.ops = &ops_1_0_0,
};
static const struct qcom_pcie_cfg ipq8064_cfg = {
.ops = &ops_2_1_0,
};
static const struct qcom_pcie_cfg msm8996_cfg = {
.ops = &ops_2_3_2,
};
static const struct qcom_pcie_cfg ipq8074_cfg = {
.ops = &ops_2_3_3,
};
static const struct qcom_pcie_cfg ipq4019_cfg = {
.ops = &ops_2_4_0,
};
static const struct qcom_pcie_cfg sdm845_cfg = {
.ops = &ops_2_7_0,
};
static const struct qcom_pcie_cfg sm8250_cfg = {
.ops = &ops_1_9_0,
};
static const struct qcom_pcie_cfg sc7280_cfg = {
.ops = &ops_1_9_0,
.pipe_clk_need_muxing = true,
};
static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = qcom_pcie_link_up,
.start_link = qcom_pcie_start_link,
......@@ -1467,6 +1531,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
struct pcie_port *pp;
struct dw_pcie *pci;
struct qcom_pcie *pcie;
const struct qcom_pcie_cfg *pcie_cfg;
int ret;
pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
......@@ -1488,7 +1553,14 @@ static int qcom_pcie_probe(struct platform_device *pdev)
pcie->pci = pci;
pcie->ops = of_device_get_match_data(dev);
pcie_cfg = of_device_get_match_data(dev);
if (!pcie_cfg || !pcie_cfg->ops) {
dev_err(dev, "Invalid platform data\n");
return -EINVAL;
}
pcie->ops = pcie_cfg->ops;
pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing;
pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
if (IS_ERR(pcie->reset)) {
......@@ -1545,16 +1617,18 @@ static int qcom_pcie_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
{ .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
{ .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
{ .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
{ .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
{ .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
{ .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
{ .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg },
{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
{ }
};
......
drivers/pci/controller/dwc/pcie-uniphier.c
View file @ 0c5c62dd
......@@ -168,30 +168,21 @@ static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
}
static void uniphier_pcie_irq_ack(struct irq_data *d)
{
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
u32 val;
val = readl(priv->base + PCL_RCV_INTX);
val &= ~PCL_RCV_INTX_ALL_STATUS;
val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_STATUS_SHIFT);
writel(val, priv->base + PCL_RCV_INTX);
}
static void uniphier_pcie_irq_mask(struct irq_data *d)
{
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&pp->lock, flags);
val = readl(priv->base + PCL_RCV_INTX);
val &= ~PCL_RCV_INTX_ALL_MASK;
val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
writel(val, priv->base + PCL_RCV_INTX);
raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static void uniphier_pcie_irq_unmask(struct irq_data *d)
......@@ -199,17 +190,20 @@ static void uniphier_pcie_irq_unmask(struct irq_data *d)
struct pcie_port *pp = irq_data_get_irq_chip_data(d);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
unsigned long flags;
u32 val;
raw_spin_lock_irqsave(&pp->lock, flags);
val = readl(priv->base + PCL_RCV_INTX);
val &= ~PCL_RCV_INTX_ALL_MASK;
val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
writel(val, priv->base + PCL_RCV_INTX);
raw_spin_unlock_irqrestore(&pp->lock, flags);
}
static struct irq_chip uniphier_pcie_irq_chip = {
.name = "PCI",
.irq_ack = uniphier_pcie_irq_ack,
.irq_mask = uniphier_pcie_irq_mask,
.irq_unmask = uniphier_pcie_irq_unmask,
};
......
drivers/pci/controller/dwc/pcie-visconti.c
View file @ 0c5c62dd
......@@ -279,13 +279,10 @@ static int visconti_add_pcie_port(struct visconti_pcie *pcie,
{
struct dw_pcie *pci = &pcie->pci;
struct pcie_port *pp = &pci->pp;
struct device *dev = &pdev->dev;
pp->irq = platform_get_irq_byname(pdev, "intr");
if (pp->irq < 0) {
dev_err(dev, "Interrupt intr is missing");
if (pp->irq < 0)
return pp->irq;
}
pp->ops = &visconti_pcie_host_ops;
......
drivers/pci/controller/pci-aardvark.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/controller/pci-hyperv.c
View file @ 0c5c62dd
......@@ -3126,14 +3126,14 @@ static int hv_pci_probe(struct hv_device *hdev,
if (dom == HVPCI_DOM_INVALID) {
dev_err(&hdev->device,
"Unable to use dom# 0x%hx or other numbers", dom_req);
"Unable to use dom# 0x%x or other numbers", dom_req);
ret = -EINVAL;
goto free_bus;
}
if (dom != dom_req)
dev_info(&hdev->device,
"PCI dom# 0x%hx has collision, using 0x%hx",
"PCI dom# 0x%x has collision, using 0x%x",
dom_req, dom);
hbus->bridge->domain_nr = dom;
......
drivers/pci/controller/pci-thunder-ecam.c
View file @ 0c5c62dd
......@@ -17,7 +17,7 @@ static void set_val(u32 v, int where, int size, u32 *val)
{
int shift = (where & 3) * 8;
pr_debug("set_val %04x: %08x\n", (unsigned)(where & ~3), v);
pr_debug("set_val %04x: %08x\n", (unsigned int)(where & ~3), v);
v >>= shift;
if (size == 1)
v &= 0xff;
......@@ -187,7 +187,7 @@ static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
pr_debug("%04x:%04x - Fix pass#: %08x, where: %03x, devfn: %03x\n",
vendor_device & 0xffff, vendor_device >> 16, class_rev,
(unsigned) where, devfn);
(unsigned int)where, devfn);
/* Check for non type-00 header */
if (cfg_type == 0) {
......
drivers/pci/controller/pci-xgene-msi.c
View file @ 0c5c62dd
......@@ -302,7 +302,7 @@ static void xgene_msi_isr(struct irq_desc *desc)
/*
* MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt
* If bit x of this register is set (x is 0..7), one or more interupts
* If bit x of this register is set (x is 0..7), one or more interrupts
* corresponding to MSInIRx is set.
*/
grp_select = xgene_msi_int_read(xgene_msi, msi_grp);
......
drivers/pci/controller/pci-xgene.c
View file @ 0c5c62dd
......@@ -48,7 +48,6 @@
#define EN_COHERENCY 0xF0000000
#define EN_REG 0x00000001
#define OB_LO_IO 0x00000002
#define XGENE_PCIE_VENDORID 0x10E8
#define XGENE_PCIE_DEVICEID 0xE004
#define SZ_1T (SZ_1G*1024ULL)
#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)
......@@ -560,7 +559,7 @@ static int xgene_pcie_setup(struct xgene_pcie_port *port)
xgene_pcie_clear_config(port);
/* setup the vendor and device IDs correctly */
val = (XGENE_PCIE_DEVICEID << 16) | XGENE_PCIE_VENDORID;
val = (XGENE_PCIE_DEVICEID << 16) | PCI_VENDOR_ID_AMCC;
xgene_pcie_writel(port, BRIDGE_CFG_0, val);
ret = xgene_pcie_map_ranges(port);
......
drivers/pci/controller/pcie-apple.c 0 → 100644
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/controller/pcie-brcmstb.c
View file @ 0c5c62dd
......@@ -145,7 +145,7 @@
#define BRCM_INT_PCI_MSI_LEGACY_NR 8
#define BRCM_INT_PCI_MSI_SHIFT 0
/* MSI target adresses */
/* MSI target addresses */
#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
......
drivers/pci/controller/pcie-iproc.c
View file @ 0c5c62dd
......@@ -249,7 +249,7 @@ enum iproc_pcie_reg {
/*
* To hold the address of the register where the MSI writes are
* programed. When ARM GICv3 ITS is used, this should be programmed
* programmed. When ARM GICv3 ITS is used, this should be programmed
* with the address of the GITS_TRANSLATER register.
*/
IPROC_PCIE_MSI_ADDR_LO,
......
drivers/staging/mt7621-pci/pci-mt7621.c → drivers/pci/controller/pcie-mt7621.c
View file @ 0c5c62dd
......@@ -30,18 +30,18 @@
#include <linux/reset.h>
#include <linux/sys_soc.h>
/* MediaTek specific configuration registers */
/* MediaTek-specific configuration registers */
#define PCIE_FTS_NUM 0x70c
#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
/* Host-PCI bridge registers */
#define RALINK_PCI_PCICFG_ADDR 0x0000
#define RALINK_PCI_PCIMSK_ADDR 0x000C
#define RALINK_PCI_PCIMSK_ADDR 0x000c
#define RALINK_PCI_CONFIG_ADDR 0x0020
#define RALINK_PCI_CONFIG_DATA 0x0024
#define RALINK_PCI_MEMBASE 0x0028
#define RALINK_PCI_IOBASE 0x002C
#define RALINK_PCI_IOBASE 0x002c
/* PCIe RC control registers */
#define RALINK_PCI_ID 0x0030
......@@ -132,7 +132,7 @@ static inline void pcie_port_write(struct mt7621_pcie_port *port,
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
unsigned int func, unsigned int where)
{
return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
(func << 8) | (where & 0xfc) | 0x80000000;
}
......@@ -217,7 +217,7 @@ static int setup_cm_memory_region(struct pci_host_bridge *host)
entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
if (!entry) {
dev_err(dev, "Cannot get memory resource\n");
dev_err(dev, "cannot get memory resource\n");
return -EINVAL;
}
......@@ -280,7 +280,7 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
GPIOD_OUT_LOW);
if (IS_ERR(port->gpio_rst)) {
dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
err = PTR_ERR(port->gpio_rst);
goto remove_reset;
}
......@@ -409,7 +409,7 @@ static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
err = mt7621_pcie_init_port(port);
if (err) {
dev_err(dev, "Initiating port %d failed\n", slot);
dev_err(dev, "initializing port %d failed\n", slot);
list_del(&port->list);
}
}
......@@ -476,7 +476,7 @@ static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
if (!entry) {
dev_err(dev, "Cannot get io resource\n");
dev_err(dev, "cannot get io resource\n");
return -EINVAL;
}
......@@ -541,25 +541,25 @@ static int mt7621_pci_probe(struct platform_device *pdev)
err = mt7621_pcie_parse_dt(pcie);
if (err) {
dev_err(dev, "Parsing DT failed\n");
dev_err(dev, "parsing DT failed\n");
return err;
}
err = mt7621_pcie_init_ports(pcie);
if (err) {
dev_err(dev, "Nothing connected in virtual bridges\n");
dev_err(dev, "nothing connected in virtual bridges\n");
return 0;
}
err = mt7621_pcie_enable_ports(bridge);
if (err) {
dev_err(dev, "Error enabling pcie ports\n");
dev_err(dev, "error enabling pcie ports\n");
goto remove_resets;
}
err = setup_cm_memory_region(bridge);
if (err) {
dev_err(dev, "Error setting up iocu mem regions\n");
dev_err(dev, "error setting up iocu mem regions\n");
goto remove_resets;
}
......
drivers/pci/controller/pcie-rcar-ep.c
View file @ 0c5c62dd
......@@ -6,16 +6,13 @@
* Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/pci.h>
#include <linux/pci-epc.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include "pcie-rcar.h"
......
drivers/pci/controller/pcie-rcar-host.c
View file @ 0c5c62dd
......@@ -24,13 +24,11 @@
#include <linux/msi.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include "pcie-rcar.h"
......
drivers/pci/controller/vmd.c
View file @ 0c5c62dd
......@@ -6,6 +6,7 @@
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/iommu.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
......@@ -18,8 +19,6 @@
#include <linux/rcupdate.h>
#include <asm/irqdomain.h>
#include <asm/device.h>
#include <asm/msi.h>
#define VMD_CFGBAR 0
#define VMD_MEMBAR1 2
......@@ -70,6 +69,8 @@ enum vmd_features {
VMD_FEAT_CAN_BYPASS_MSI_REMAP = (1 << 4),
};
static DEFINE_IDA(vmd_instance_ida);
/*
* Lock for manipulating VMD IRQ lists.
*/
......@@ -120,6 +121,8 @@ struct vmd_dev {
struct pci_bus *bus;
u8 busn_start;
u8 first_vec;
char *name;
int instance;
};
static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus)
......@@ -650,7 +653,7 @@ static int vmd_alloc_irqs(struct vmd_dev *vmd)
INIT_LIST_HEAD(&vmd->irqs[i].irq_list);
err = devm_request_irq(&dev->dev, pci_irq_vector(dev, i),
vmd_irq, IRQF_NO_THREAD,
"vmd", &vmd->irqs[i]);
vmd->name, &vmd->irqs[i]);
if (err)
return err;
}
......@@ -761,7 +764,8 @@ static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
* acceptable because the guest is usually CPU-limited and MSI
* remapping doesn't become a performance bottleneck.
*/
if (!(features & VMD_FEAT_CAN_BYPASS_MSI_REMAP) ||
if (iommu_capable(vmd->dev->dev.bus, IOMMU_CAP_INTR_REMAP) ||
!(features & VMD_FEAT_CAN_BYPASS_MSI_REMAP) ||
offset[0] || offset[1]) {
ret = vmd_alloc_irqs(vmd);
if (ret)
......@@ -834,18 +838,32 @@ static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
return -ENOMEM;
vmd->dev = dev;
vmd->instance = ida_simple_get(&vmd_instance_ida, 0, 0, GFP_KERNEL);
if (vmd->instance < 0)
return vmd->instance;
vmd->name = kasprintf(GFP_KERNEL, "vmd%d", vmd->instance);
if (!vmd->name) {
err = -ENOMEM;
goto out_release_instance;
}
err = pcim_enable_device(dev);
if (err < 0)
return err;
goto out_release_instance;
vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0);
if (!vmd->cfgbar)
return -ENOMEM;
if (!vmd->cfgbar) {
err = -ENOMEM;
goto out_release_instance;
}
pci_set_master(dev);
if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) &&
dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)))
return -ENODEV;
dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32))) {
err = -ENODEV;
goto out_release_instance;
}
if (features & VMD_FEAT_OFFSET_FIRST_VECTOR)
vmd->first_vec = 1;
......@@ -854,11 +872,16 @@ static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
pci_set_drvdata(dev, vmd);
err = vmd_enable_domain(vmd, features);
if (err)
return err;
goto out_release_instance;
dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n",
vmd->sysdata.domain);
return 0;
out_release_instance:
ida_simple_remove(&vmd_instance_ida, vmd->instance);
kfree(vmd->name);
return err;
}
static void vmd_cleanup_srcu(struct vmd_dev *vmd)
......@@ -879,6 +902,8 @@ static void vmd_remove(struct pci_dev *dev)
vmd_cleanup_srcu(vmd);
vmd_detach_resources(vmd);
vmd_remove_irq_domain(vmd);
ida_simple_remove(&vmd_instance_ida, vmd->instance);
kfree(vmd->name);
}
#ifdef CONFIG_PM_SLEEP
......@@ -903,7 +928,7 @@ static int vmd_resume(struct device *dev)
for (i = 0; i < vmd->msix_count; i++) {
err = devm_request_irq(dev, pci_irq_vector(pdev, i),
vmd_irq, IRQF_NO_THREAD,
"vmd", &vmd->irqs[i]);
vmd->name, &vmd->irqs[i]);
if (err)
return err;
}
......
drivers/pci/endpoint/functions/pci-epf-ntb.c
View file @ 0c5c62dd
......@@ -1937,7 +1937,7 @@ static ssize_t epf_ntb_##_name##_show(struct config_item *item, \
struct config_group *group = to_config_group(item); \
struct epf_ntb *ntb = to_epf_ntb(group); \
\
return sprintf(page, "%d\n", ntb->_name); \
return sysfs_emit(page, "%d\n", ntb->_name); \
}
#define EPF_NTB_W(_name) \
......@@ -1947,11 +1947,9 @@ static ssize_t epf_ntb_##_name##_store(struct config_item *item, \
struct config_group *group = to_config_group(item); \
struct epf_ntb *ntb = to_epf_ntb(group); \
u32 val; \
int ret; \
\
ret = kstrtou32(page, 0, &val); \
if (ret) \
return ret; \
if (kstrtou32(page, 0, &val) < 0) \
return -EINVAL; \
\
ntb->_name = val; \
\
......@@ -1968,7 +1966,7 @@ static ssize_t epf_ntb_##_name##_show(struct config_item *item, \
\
sscanf(#_name, "mw%d", &win_no); \
\
return sprintf(page, "%lld\n", ntb->mws_size[win_no - 1]); \
return sysfs_emit(page, "%lld\n", ntb->mws_size[win_no - 1]); \
}
#define EPF_NTB_MW_W(_name) \
......@@ -1980,11 +1978,9 @@ static ssize_t epf_ntb_##_name##_store(struct config_item *item, \
struct device *dev = &ntb->epf->dev; \
int win_no; \
u64 val; \
int ret; \
\
ret = kstrtou64(page, 0, &val); \
if (ret) \
return ret; \
if (kstrtou64(page, 0, &val) < 0) \
return -EINVAL; \
\
if (sscanf(#_name, "mw%d", &win_no) != 1) \
return -EINVAL; \
......@@ -2005,11 +2001,9 @@ static ssize_t epf_ntb_num_mws_store(struct config_item *item,
struct config_group *group = to_config_group(item);
struct epf_ntb *ntb = to_epf_ntb(group);
u32 val;
int ret;
ret = kstrtou32(page, 0, &val);
if (ret)
return ret;
if (kstrtou32(page, 0, &val) < 0)
return -EINVAL;
if (val > MAX_MW)
return -EINVAL;
......
drivers/pci/endpoint/pci-ep-cfs.c
View file @ 0c5c62dd
......@@ -175,9 +175,8 @@ static ssize_t pci_epc_start_store(struct config_item *item, const char *page,
epc = epc_group->epc;
ret = kstrtobool(page, &start);
if (ret)
return ret;
if (kstrtobool(page, &start) < 0)
return -EINVAL;
if (!start) {
pci_epc_stop(epc);
......@@ -198,8 +197,7 @@ static ssize_t pci_epc_start_store(struct config_item *item, const char *page,
static ssize_t pci_epc_start_show(struct config_item *item, char *page)
{
return sprintf(page, "%d\n",
to_pci_epc_group(item)->start);
return sysfs_emit(page, "%d\n", to_pci_epc_group(item)->start);
}
CONFIGFS_ATTR(pci_epc_, start);
......@@ -321,7 +319,7 @@ static ssize_t pci_epf_##_name##_show(struct config_item *item, char *page) \
struct pci_epf *epf = to_pci_epf_group(item)->epf; \
if (WARN_ON_ONCE(!epf->header)) \
return -EINVAL; \
return sprintf(page, "0x%04x\n", epf->header->_name); \
return sysfs_emit(page, "0x%04x\n", epf->header->_name); \
}
#define PCI_EPF_HEADER_W_u32(_name) \
......@@ -329,13 +327,11 @@ static ssize_t pci_epf_##_name##_store(struct config_item *item, \
const char *page, size_t len) \
{ \
u32 val; \
int ret; \
struct pci_epf *epf = to_pci_epf_group(item)->epf; \
if (WARN_ON_ONCE(!epf->header)) \
return -EINVAL; \
ret = kstrtou32(page, 0, &val); \
if (ret) \
return ret; \
if (kstrtou32(page, 0, &val) < 0) \
return -EINVAL; \
epf->header->_name = val; \
return len; \
}
......@@ -345,13 +341,11 @@ static ssize_t pci_epf_##_name##_store(struct config_item *item, \
const char *page, size_t len) \
{ \
u16 val; \
int ret; \
struct pci_epf *epf = to_pci_epf_group(item)->epf; \
if (WARN_ON_ONCE(!epf->header)) \
return -EINVAL; \
ret = kstrtou16(page, 0, &val); \
if (ret) \
return ret; \
if (kstrtou16(page, 0, &val) < 0) \
return -EINVAL; \
epf->header->_name = val; \
return len; \
}
......@@ -361,13 +355,11 @@ static ssize_t pci_epf_##_name##_store(struct config_item *item, \
const char *page, size_t len) \
{ \
u8 val; \
int ret; \
struct pci_epf *epf = to_pci_epf_group(item)->epf; \
if (WARN_ON_ONCE(!epf->header)) \
return -EINVAL; \
ret = kstrtou8(page, 0, &val); \
if (ret) \
return ret; \
if (kstrtou8(page, 0, &val) < 0) \
return -EINVAL; \
epf->header->_name = val; \
return len; \
}
......@@ -376,11 +368,9 @@ static ssize_t pci_epf_msi_interrupts_store(struct config_item *item,
const char *page, size_t len)
{
u8 val;
int ret;
ret = kstrtou8(page, 0, &val);
if (ret)
return ret;
if (kstrtou8(page, 0, &val) < 0)
return -EINVAL;
to_pci_epf_group(item)->epf->msi_interrupts = val;
......@@ -390,19 +380,17 @@ static ssize_t pci_epf_msi_interrupts_store(struct config_item *item,
static ssize_t pci_epf_msi_interrupts_show(struct config_item *item,
char *page)
{
return sprintf(page, "%d\n",
to_pci_epf_group(item)->epf->msi_interrupts);
return sysfs_emit(page, "%d\n",
to_pci_epf_group(item)->epf->msi_interrupts);
}
static ssize_t pci_epf_msix_interrupts_store(struct config_item *item,
const char *page, size_t len)
{
u16 val;
int ret;
ret = kstrtou16(page, 0, &val);
if (ret)
return ret;
if (kstrtou16(page, 0, &val) < 0)
return -EINVAL;
to_pci_epf_group(item)->epf->msix_interrupts = val;
......@@ -412,8 +400,8 @@ static ssize_t pci_epf_msix_interrupts_store(struct config_item *item,
static ssize_t pci_epf_msix_interrupts_show(struct config_item *item,
char *page)
{
return sprintf(page, "%d\n",
to_pci_epf_group(item)->epf->msix_interrupts);
return sysfs_emit(page, "%d\n",
to_pci_epf_group(item)->epf->msix_interrupts);
}
PCI_EPF_HEADER_R(vendorid)
......
drivers/pci/endpoint/pci-epc-core.c
View file @ 0c5c62dd
......@@ -700,7 +700,7 @@ EXPORT_SYMBOL_GPL(pci_epc_linkup);
/**
* pci_epc_init_notify() - Notify the EPF device that EPC device's core
* initialization is completed.
* @epc: the EPC device whose core initialization is completeds
* @epc: the EPC device whose core initialization is completed
*
* Invoke to Notify the EPF device that the EPC device's initialization
* is completed.
......
drivers/pci/endpoint/pci-epf-core.c
View file @ 0c5c62dd
......@@ -224,7 +224,7 @@ EXPORT_SYMBOL_GPL(pci_epf_add_vepf);
* be removed
* @epf_vf: the virtual EP function to be removed
*
* Invoke to remove a virtual endpoint function from the physcial endpoint
* Invoke to remove a virtual endpoint function from the physical endpoint
* function.
*/
void pci_epf_remove_vepf(struct pci_epf *epf_pf, struct pci_epf *epf_vf)
......@@ -432,7 +432,7 @@ EXPORT_SYMBOL_GPL(pci_epf_destroy);
/**
* pci_epf_create() - create a new PCI EPF device
* @name: the name of the PCI EPF device. This name will be used to bind the
* the EPF device to a EPF driver
* EPF device to a EPF driver
*
* Invoke to create a new PCI EPF device by providing the name of the function
* device.
......
drivers/pci/hotplug/acpiphp_glue.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/hotplug/cpqphp.h
View file @ 0c5c62dd
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drivers/pci/hotplug/cpqphp_ctrl.c
View file @ 0c5c62dd
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drivers/pci/hotplug/cpqphp_pci.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/hotplug/ibmphp.h
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/hotplug/pciehp.h
View file @ 0c5c62dd
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drivers/pci/hotplug/pciehp_core.c
View file @ 0c5c62dd
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drivers/pci/hotplug/pciehp_hpc.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/hotplug/shpchp_hpc.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/iov.c
View file @ 0c5c62dd
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drivers/pci/msi.c
View file @ 0c5c62dd
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drivers/pci/of.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/p2pdma.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/pci-bridge-emul.c
View file @ 0c5c62dd
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drivers/pci/pci-driver.c
View file @ 0c5c62dd
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drivers/pci/pci-sysfs.c
View file @ 0c5c62dd
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drivers/pci/pci.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/pci.h
View file @ 0c5c62dd
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drivers/pci/pcie/Makefile
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drivers/pci/pcie/aer.c
View file @ 0c5c62dd
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drivers/pci/pcie/aspm.c
View file @ 0c5c62dd
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drivers/pci/pcie/err.c
View file @ 0c5c62dd
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drivers/pci/pcie/portdrv.h
View file @ 0c5c62dd
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drivers/pci/pcie/portdrv_core.c
View file @ 0c5c62dd
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drivers/pci/pcie/portdrv_pci.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/probe.c
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drivers/pci/quirks.c
View file @ 0c5c62dd
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drivers/pci/rom.c
View file @ 0c5c62dd
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drivers/pci/setup-bus.c
View file @ 0c5c62dd
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drivers/pci/setup-irq.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/pci/switch/switchtec.c
View file @ 0c5c62dd
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drivers/pci/vpd.c
View file @ 0c5c62dd
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drivers/pci/xen-pcifront.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/ssb/pcihost_wrapper.c
View file @ 0c5c62dd
This diff is collapsed.
drivers/staging/Kconfig
View file @ 0c5c62dd
This diff is collapsed.
drivers/staging/Makefile
View file @ 0c5c62dd
This diff is collapsed.
drivers/staging/mt7621-pci/Kconfig deleted 100644 → 0
View file @ 512b7931
This diff is collapsed.
drivers/staging/mt7621-pci/Makefile deleted 100644 → 0
View file @ 512b7931
This diff is collapsed.
drivers/staging/mt7621-pci/TODO deleted 100644 → 0
View file @ 512b7931
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drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt deleted 100644 → 0
View file @ 512b7931
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drivers/usb/host/xhci-pci.c
View file @ 0c5c62dd
This diff is collapsed.
include/linux/acpi.h
View file @ 0c5c62dd
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include/linux/irqdomain.h
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include/linux/pci.h
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include/linux/switchtec.h
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include/uapi/linux/pci_regs.h
View file @ 0c5c62dd
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kernel/irq/irqdomain.c
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