Commit 0d5ace1a authored by Mario Limonciello's avatar Mario Limonciello Committed by Linus Walleij

pinctrl: amd: Only use special debounce behavior for GPIO 0

It's uncommon to use debounce on any other pin, but technically
we should only set debounce to 0 when working off GPIO0.

Cc: stable@vger.kernel.org
Tested-by: default avatarJan Visser <starquake@linuxeverywhere.org>
Fixes: 968ab926 ("pinctrl: amd: Detect internal GPIO0 debounce handling")
Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230705133005.577-2-mario.limonciello@amd.comSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 06c2afb8
......@@ -128,9 +128,11 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
raw_spin_lock_irqsave(&gpio_dev->lock, flags);
/* Use special handling for Pin0 debounce */
pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
debounce = 0;
if (offset == 0) {
pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
debounce = 0;
}
pin_reg = readl(gpio_dev->base + offset * 4);
......
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