drm/amdgpu: complement the IH node_id table for multiple AIDs

With different node_id, the SDMA interrupt from multiple AIDs can be
distinguished by sw driver.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

@@ -100,12 +100,16 @@ const char *soc15_ih_clientid_name[] = {
 };
 
 const int node_id_to_phys_map[NODEID_MAX] = {
+	[AID0_NODEID] = 0,
 	[XCD0_NODEID] = 0,
 	[XCD1_NODEID] = 1,
+	[AID1_NODEID] = 1,
 	[XCD2_NODEID] = 2,
 	[XCD3_NODEID] = 3,
+	[AID2_NODEID] = 2,
 	[XCD4_NODEID] = 4,
 	[XCD5_NODEID] = 5,
+	[AID3_NODEID] = 3,
 	[XCD6_NODEID] = 6,
 	[XCD7_NODEID] = 7,
 };

drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h

@@ -102,13 +102,17 @@ struct amdgpu_irq {
 	bool                            retry_cam_enabled;
 };
 
-enum interrupt_node_id_per_xcp {
+enum interrupt_node_id_per_aid {
+	AID0_NODEID = 0,
 	XCD0_NODEID = 1,
 	XCD1_NODEID = 2,
+	AID1_NODEID = 4,
 	XCD2_NODEID = 5,
 	XCD3_NODEID = 6,
+	AID2_NODEID = 8,
 	XCD4_NODEID = 9,
 	XCD5_NODEID = 10,
+	AID3_NODEID = 12,
 	XCD6_NODEID = 13,
 	XCD7_NODEID = 14,
 	NODEID_MAX,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

@@ -1492,6 +1492,9 @@ static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
 
 	DRM_DEBUG("IH: SDMA trap\n");
 	instance = sdma_v4_4_2_irq_id_to_seq(entry->client_id);
+	instance += node_id_to_phys_map[entry->node_id] *
+			adev->sdma.num_inst_per_aid;
+
 	switch (entry->ring_id) {
 	case 0:
 		amdgpu_fence_process(&adev->sdma.instance[instance].ring);