Commit 0da3ea12 authored by Jesse Barnes's avatar Jesse Barnes Committed by Dave Airlie

drm/i915: save/restore interrupt state

On resume, if the interrupt state isn't restored correctly, we may end
up with a flood of unexpected or ill-timed interrupts, which could cause
the kernel to disable the interrupt or vblank events to happen at the
wrong time.  So save/restore them properly.
Signed-off-by: default avatarDave Airlie <airlied@linux.ie>
parent ca0b07d9
...@@ -276,6 +276,7 @@ static int i915_suspend(struct drm_device *dev) ...@@ -276,6 +276,7 @@ static int i915_suspend(struct drm_device *dev)
dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
} }
i915_save_palette(dev, PIPE_A); i915_save_palette(dev, PIPE_A);
dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
/* Pipe & plane B info */ /* Pipe & plane B info */
dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
...@@ -303,6 +304,7 @@ static int i915_suspend(struct drm_device *dev) ...@@ -303,6 +304,7 @@ static int i915_suspend(struct drm_device *dev)
dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
} }
i915_save_palette(dev, PIPE_B); i915_save_palette(dev, PIPE_B);
dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
/* CRT state */ /* CRT state */
dev_priv->saveADPA = I915_READ(ADPA); dev_priv->saveADPA = I915_READ(ADPA);
...@@ -329,6 +331,11 @@ static int i915_suspend(struct drm_device *dev) ...@@ -329,6 +331,11 @@ static int i915_suspend(struct drm_device *dev)
dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
/* Interrupt state */
dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
/* VGA state */ /* VGA state */
dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0); dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1); dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
......
...@@ -134,6 +134,7 @@ typedef struct drm_i915_private { ...@@ -134,6 +134,7 @@ typedef struct drm_i915_private {
u32 saveVBLANK_A; u32 saveVBLANK_A;
u32 saveVSYNC_A; u32 saveVSYNC_A;
u32 saveBCLRPAT_A; u32 saveBCLRPAT_A;
u32 savePIPEASTAT;
u32 saveDSPASTRIDE; u32 saveDSPASTRIDE;
u32 saveDSPASIZE; u32 saveDSPASIZE;
u32 saveDSPAPOS; u32 saveDSPAPOS;
...@@ -154,6 +155,7 @@ typedef struct drm_i915_private { ...@@ -154,6 +155,7 @@ typedef struct drm_i915_private {
u32 saveVBLANK_B; u32 saveVBLANK_B;
u32 saveVSYNC_B; u32 saveVSYNC_B;
u32 saveBCLRPAT_B; u32 saveBCLRPAT_B;
u32 savePIPEBSTAT;
u32 saveDSPBSTRIDE; u32 saveDSPBSTRIDE;
u32 saveDSPBSIZE; u32 saveDSPBSIZE;
u32 saveDSPBPOS; u32 saveDSPBPOS;
...@@ -182,6 +184,9 @@ typedef struct drm_i915_private { ...@@ -182,6 +184,9 @@ typedef struct drm_i915_private {
u32 saveFBC_LL_BASE; u32 saveFBC_LL_BASE;
u32 saveFBC_CONTROL; u32 saveFBC_CONTROL;
u32 saveFBC_CONTROL2; u32 saveFBC_CONTROL2;
u32 saveIER;
u32 saveIIR;
u32 saveIMR;
u32 saveSWF0[16]; u32 saveSWF0[16];
u32 saveSWF1[16]; u32 saveSWF1[16];
u32 saveSWF2[3]; u32 saveSWF2[3];
......
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