Commit 0e0b89c0 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/powerplay: properly set mp1 state for SW SMU suspend/reset routine

Set mp1 state properly for SW SMU suspend/reset routine.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d950800e
...@@ -2233,17 +2233,17 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) ...@@ -2233,17 +2233,17 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
/* handle putting the SMC in the appropriate state */ /* handle putting the SMC in the appropriate state */
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
if (is_support_sw_smu(adev)) { if (is_support_sw_smu(adev)) {
/* todo */ r = smu_set_mp1_state(&adev->smu, adev->mp1_state);
} else if (adev->powerplay.pp_funcs && } else if (adev->powerplay.pp_funcs &&
adev->powerplay.pp_funcs->set_mp1_state) { adev->powerplay.pp_funcs->set_mp1_state) {
r = adev->powerplay.pp_funcs->set_mp1_state( r = adev->powerplay.pp_funcs->set_mp1_state(
adev->powerplay.pp_handle, adev->powerplay.pp_handle,
adev->mp1_state); adev->mp1_state);
if (r) { }
DRM_ERROR("SMC failed to set mp1 state %d, %d\n", if (r) {
adev->mp1_state, r); DRM_ERROR("SMC failed to set mp1 state %d, %d\n",
return r; adev->mp1_state, r);
} return r;
} }
} }
......
...@@ -1788,6 +1788,46 @@ int smu_force_clk_levels(struct smu_context *smu, ...@@ -1788,6 +1788,46 @@ int smu_force_clk_levels(struct smu_context *smu,
return ret; return ret;
} }
int smu_set_mp1_state(struct smu_context *smu,
enum pp_mp1_state mp1_state)
{
uint16_t msg;
int ret;
/*
* The SMC is not fully ready. That may be
* expected as the IP may be masked.
* So, just return without error.
*/
if (!smu->pm_enabled)
return 0;
switch (mp1_state) {
case PP_MP1_STATE_SHUTDOWN:
msg = SMU_MSG_PrepareMp1ForShutdown;
break;
case PP_MP1_STATE_UNLOAD:
msg = SMU_MSG_PrepareMp1ForUnload;
break;
case PP_MP1_STATE_RESET:
msg = SMU_MSG_PrepareMp1ForReset;
break;
case PP_MP1_STATE_NONE:
default:
return 0;
}
/* some asics may not support those messages */
if (smu_msg_get_index(smu, msg) < 0)
return 0;
ret = smu_send_smc_msg(smu, msg);
if (ret)
pr_err("[PrepareMp1] Failed!\n");
return ret;
}
const struct amd_ip_funcs smu_ip_funcs = { const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu", .name = "smu",
.early_init = smu_early_init, .early_init = smu_early_init,
......
...@@ -836,5 +836,7 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask); ...@@ -836,5 +836,7 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
int smu_force_clk_levels(struct smu_context *smu, int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, enum smu_clk_type clk_type,
uint32_t mask); uint32_t mask);
int smu_set_mp1_state(struct smu_context *smu,
enum pp_mp1_state mp1_state);
#endif #endif
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