Commit 0e249898 authored by Arjun Vynipadath's avatar Arjun Vynipadath Committed by David S. Miller

cxgb4: Fix {vxlan/geneve}_port initialization

adapter->rawf_cnt was not initialized, thereby
ndo_udp_tunnel_{add/del} was returning immediately
without initializing {vxlan/geneve}_port.
Also initializes mps_encap_entry refcnt.

Fixes: 846eac3f ("cxgb4: implement udp tunnel callbacks")
Signed-off-by: default avatarArjun Vynipadath <arjun@chelsio.com>
Signed-off-by: default avatarGanesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f4a313b9
...@@ -4276,6 +4276,20 @@ static int adap_init0(struct adapter *adap) ...@@ -4276,6 +4276,20 @@ static int adap_init0(struct adapter *adap)
adap->tids.nftids = val[4] - val[3] + 1; adap->tids.nftids = val[4] - val[3] + 1;
adap->sge.ingr_start = val[5]; adap->sge.ingr_start = val[5];
if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
/* Read the raw mps entries. In T6, the last 2 tcam entries
* are reserved for raw mac addresses (rawf = 2, one per port).
*/
params[0] = FW_PARAM_PFVF(RAWF_START);
params[1] = FW_PARAM_PFVF(RAWF_END);
ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
params, val);
if (ret == 0) {
adap->rawf_start = val[0];
adap->rawf_cnt = val[1] - val[0] + 1;
}
}
/* qids (ingress/egress) returned from firmware can be anywhere /* qids (ingress/egress) returned from firmware can be anywhere
* in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
* Hence driver needs to allocate memory for this range to * Hence driver needs to allocate memory for this range to
...@@ -5181,6 +5195,7 @@ static void free_some_resources(struct adapter *adapter) ...@@ -5181,6 +5195,7 @@ static void free_some_resources(struct adapter *adapter)
{ {
unsigned int i; unsigned int i;
kvfree(adapter->mps_encap);
kvfree(adapter->smt); kvfree(adapter->smt);
kvfree(adapter->l2t); kvfree(adapter->l2t);
kvfree(adapter->srq); kvfree(adapter->srq);
...@@ -5677,6 +5692,12 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -5677,6 +5692,12 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
adapter->params.offload = 0; adapter->params.offload = 0;
} }
adapter->mps_encap = kvzalloc(sizeof(struct mps_encap_entry) *
adapter->params.arch.mps_tcam_size,
GFP_KERNEL);
if (!adapter->mps_encap)
dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n");
#if IS_ENABLED(CONFIG_IPV6) #if IS_ENABLED(CONFIG_IPV6)
if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) && if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
(!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
......
...@@ -1305,6 +1305,8 @@ enum fw_params_param_pfvf { ...@@ -1305,6 +1305,8 @@ enum fw_params_param_pfvf {
FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
}; };
......
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