Skip to content

L
linux
Commit 0e2c9884 authored by Stephen Boyd's avatar Stephen Boyd
Browse files
Options

Merge branches 'clk-mediatek', 'clk-trace', 'clk-qcom' and 'clk-microchip' into clk-next 

 - Tracepoints for clk_rate_request structures

* clk-mediatek:
  clk: mediatek: fix dependency of MT7986 ADC clocks
  clk: mediatek: Change PLL register API for MT8186
  clk: mediatek: Add new clock driver to handle FHCTL hardware
  dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping
  clk: mediatek: Export PLL operations symbols
  clk: mediatek: mt8186-topckgen: Add GPU clock mux notifier
  clk: mediatek: mt8186-mfg: Propagate rate changes to parent
  clk: mediatek: mt8195-topckgen: Drop flags for main/univpll fixed factors
  clk: mediatek: mt8192: Drop flags for main/univpll fixed factors
  clk: mediatek: mt6795-topckgen: Drop flags for main/sys/univpll fixed factors
  clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factors
  clk: mediatek: mt8183: Drop flags for sys/univpll fixed factors
  clk: mediatek: mt8183: Compress top_divs array entries
  clk: mediatek: mt8186-topckgen: Drop flags for main/univpll fixed factors
  clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks

* clk-trace:
  clk: Add trace events for rate requests
  clk: Store clk_core for clk_rate_request

* clk-qcom: (69 commits)
  clk: qcom: rpmh: add support for SM6350 rpmh IPA clock
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file
  clk: qcom: gcc-ipq4019: switch to devm_clk_notifier_register
  clk: qcom: rpmh: remove usage of platform name
  clk: qcom: rpmh: rename VRM clock data
  clk: qcom: rpmh: rename ARC clock data
  clk: qcom: rpmh: support separate symbol name for the RPMH clocks
  clk: qcom: rpmh: remove platform names from BCM clocks
  clk: qcom: rpmh: drop all _ao names
  clk: qcom: rpmh: reuse common duplicate clocks
  clk: qcom: rpmh: group clock definitions together
  clk: qcom: rpm: drop the platform from clock definitions
  clk: qcom: rpm: drop the _clk suffix completely
  ...

* clk-microchip:
  clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
  clk: microchip: check for null return of devm_kzalloc()
parents e0a1d139 503fa6d1 49e62e0d 63cd992e 3c79ace9
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 11799 additions and 2910 deletions
Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml 0 → 100644
View file @ 0e2c9884
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek frequency hopping and spread spectrum clocking control
maintainers:
- Edward-JW Yang <edward-jw.yang@mediatek.com>
description: |
Frequency hopping control (FHCTL) is a piece of hardware that control
some PLLs to adopt "hopping" mechanism to adjust their frequency.
Spread spectrum clocking (SSC) is another function provided by this hardware.
properties:
compatible:
const: mediatek,mt8186-fhctl
reg:
maxItems: 1
clocks:
description: Phandles of the PLL with FHCTL hardware capability.
minItems: 1
maxItems: 30
mediatek,hopping-ssc-percent:
description: The percentage of spread spectrum clocking for one PLL.
minItems: 1
maxItems: 30
items:
default: 0
minimum: 0
maximum: 8
required:
- compatible
- reg
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8186-clk.h>
fhctl: fhctl@1000ce00 {
compatible = "mediatek,mt8186-fhctl";
reg = <0x1000ce00 0x200>;
clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
mediatek,hopping-ssc-percent = <3>;
};
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View file @ 0e2c9884
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm A53 PLL Binding
title: Qualcomm A53 PLL clock
maintainers:
- Bjorn Andersson <andersson@kernel.org>
......
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
View file @ 0e2c9884
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm A7 PLL Binding
title: Qualcomm A7 PLL clock
maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
......
Documentation/devicetree/bindings/clock/qcom,aoncc-sm8250.yaml
View file @ 0e2c9884
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for LPASS Always ON Clock Controller on SM8250 SoCs
title: LPASS Always ON Clock Controller on SM8250 SoCs
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
......@@ -17,7 +17,7 @@ description: |
properties:
compatible:
const: qcom,sm8250-lpass-aon
const: qcom,sm8250-lpass-aoncc
reg:
maxItems: 1
......@@ -28,11 +28,13 @@ properties:
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio codec voting clock
- description: Glitch Free Mux register clock
clock-names:
items:
- const: core
- const: audio
- const: bus
required:
......@@ -50,9 +52,10 @@ examples:
#include <dt-bindings/sound/qcom,q6afe.h>
clock-controller@3800000 {
#clock-cells = <1>;
compatible = "qcom,sm8250-lpass-aon";
compatible = "qcom,sm8250-lpass-aoncc";
reg = <0x03380000 0x40000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "bus";
clock-names = "core", "audio", "bus";
};
Documentation/devicetree/bindings/clock/qcom,audiocc-sm8250.yaml
View file @ 0e2c9884
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock bindings for LPASS Audio Clock Controller on SM8250 SoCs
title: LPASS Audio Clock Controller on SM8250 SoCs
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
......@@ -28,11 +28,13 @@ properties:
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio codec voting clock
- description: Glitch Free Mux register clock
clock-names:
items:
- const: core
- const: audio
- const: bus
required:
......@@ -53,6 +55,7 @@ examples:
compatible = "qcom,sm8250-lpass-audiocc";
reg = <0x03300000 0x30000>;
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core", "bus";
clock-names = "core", "audio", "bus";
};
Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
title: Qualcomm Camera Clock & Reset Controller on SM8250
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
Qualcomm camera clock control module provides the clocks, resets and
power domains on SM8250.
See also dt-bindings/clock/qcom,camcc-sm8250.h
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml 0 → 100644
View file @ 0e2c9884
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains for the two MDSS instances on SC8280XP.
See also:
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
properties:
compatible:
enum:
- qcom,sc8280xp-dispcc0
- qcom,sc8280xp-dispcc1
clocks:
items:
- description: AHB interface clock,
- description: SoC CXO clock
- description: SoC sleep clock
- description: DisplayPort 0 link clock
- description: DisplayPort 0 VCO div clock
- description: DisplayPort 1 link clock
- description: DisplayPort 1 VCO div clock
- description: DisplayPort 2 link clock
- description: DisplayPort 2 VCO div clock
- description: DisplayPort 3 link clock
- description: DisplayPort 3 VCO div clock
- description: DSI 0 PLL byte clock
- description: DSI 0 PLL DSI clock
- description: DSI 1 PLL byte clock
- description: DSI 1 PLL DSI clock
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
items:
- description: MMCX power domain
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@af00000 {
compatible = "qcom,sc8280xp-dispcc0";
reg = <0x0af00000 0x20000>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&mdss0_dp_phy0 0>,
<&mdss0_dp_phy0 1>,
<&mdss0_dp_phy1 0>,
<&mdss0_dp_phy1 1>,
<&mdss0_dp_phy2 0>,
<&mdss0_dp_phy2 1>,
<&mdss0_dp_phy3 0>,
<&mdss0_dp_phy3 1>,
<&mdss0_dsi0_phy 0>,
<&mdss0_dsi0_phy 1>,
<&mdss0_dsi1_phy 0>,
<&mdss0_dsi1_phy 1>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock Controller Binding for SM6125
title: Qualcomm Display Clock Controller on SM6125
maintainers:
- Martin Botka <martin.botka@somainline.org>
description: |
Qualcomm display clock control module which supports the clocks and
power domains on SM6125.
Qualcomm display clock control module provides the clocks and power domains
on SM6125.
See also:
dt-bindings/clock/qcom,dispcc-sm6125.h
See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SM6350
title: Qualcomm Display Clock & Reset Controller on SM6350
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM6350.
Qualcomm display clock control module provides the clocks, resets and power
domains on SM6350.
See also dt-bindings/clock/qcom,dispcc-sm6350.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
View file @ 0e2c9884
......@@ -4,19 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
maintainers:
- Jonathan Marek <jonathan@marek.ca>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM8150/SM8250/SM8350.
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8150/SM8250/SM8350.
See also:
dt-bindings/clock/qcom,dispcc-sm8150.h
dt-bindings/clock/qcom,dispcc-sm8250.h
dt-bindings/clock/qcom,dispcc-sm8350.h
See also::
include/dt-bindings/clock/qcom,dispcc-sm8150.h
include/dt-bindings/clock/qcom,dispcc-sm8250.h
include/dt-bindings/clock/qcom,dispcc-sm8350.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
View file @ 0e2c9884
......@@ -4,22 +4,22 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960
allOf:
- $ref: qcom,gcc.yaml#
title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on APQ8064.
Qualcomm global clock control module provides the clocks, resets and power
domains on APQ8064.
See also:
- dt-bindings/clock/qcom,gcc-msm8960.h
- dt-bindings/reset/qcom,gcc-msm8960.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8960.h
include/dt-bindings/reset/qcom,gcc-msm8960.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
View file @ 0e2c9884
......@@ -4,19 +4,19 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
title: Qualcomm Global Clock & Reset Controller on APQ8084
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on APQ8084.
Qualcomm global clock control module provides the clocks, resets and power
domains on APQ8084.
See also::
- dt-bindings/clock/qcom,gcc-apq8084.h
- dt-bindings/reset/qcom,gcc-apq8084.h
include/dt-bindings/clock/qcom,gcc-apq8084.h
include/dt-bindings/reset/qcom,gcc-apq8084.h
allOf:
- $ref: qcom,gcc.yaml#
......
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
View file @ 0e2c9884
......@@ -4,21 +4,21 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
allOf:
- $ref: qcom,gcc.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ8064
maintainers:
- Ansuel Smith <ansuelsmth@gmail.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on IPQ8064.
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8064.
See also:
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
See also::
include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
......@@ -27,14 +27,18 @@ properties:
- const: syscon
clocks:
minItems: 2
items:
- description: PXO source
- description: CXO source
- description: PLL4 from LCC
clock-names:
minItems: 2
items:
- const: pxo
- const: cxo
- const: pll4
thermal-sensor:
type: object
......@@ -51,13 +55,14 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
gcc: clock-controller@900000 {
compatible = "qcom,gcc-ipq8064", "syscon";
reg = <0x00900000 0x4000>;
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
clock-names = "pxo", "cxo", "pll4";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
......
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
View file @ 0e2c9884
......@@ -4,47 +4,39 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074
title: Qualcomm Global Clock & Reset Controller on IPQ8074
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on IPQ8074.
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8074.
See also:
- dt-bindings/clock/qcom,gcc-ipq8074.h
See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,gcc-ipq8074
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
'#reset-cells':
const: 1
reg:
maxItems: 1
clocks:
items:
- description: board XO clock
- description: sleep clock
protected-clocks:
description:
Protected clock specifier list as per common clock binding.
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
- reg
- '#clock-cells'
- '#power-domain-cells'
- '#reset-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |
......
Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml
View file @ 0e2c9884
......@@ -4,22 +4,22 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8660
title: Qualcomm Global Clock & Reset Controller on MSM8660
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks and resets on
Qualcomm global clock control module provides the clocks and resets on
MSM8660
See also:
- dt-bindings/clock/qcom,gcc-msm8660.h
- dt-bindings/reset/qcom,gcc-msm8660.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8660.h
include/dt-bindings/reset/qcom,gcc-msm8660.h
allOf:
- $ref: "qcom,gcc.yaml#"
- $ref: qcom,gcc.yaml#
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8909
title: Qualcomm Global Clock & Reset Controller on MSM8909
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8909.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8909.
See also:
- dt-bindings/clock/qcom,gcc-msm8909.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
View file @ 0e2c9884
......@@ -4,21 +4,21 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8916 or MSM8939.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8916 or MSM8939.
See also:
- dt-bindings/clock/qcom,gcc-msm8916.h
- dt-bindings/clock/qcom,gcc-msm8939.h
- dt-bindings/reset/qcom,gcc-msm8916.h
- dt-bindings/reset/qcom,gcc-msm8939.h
See also::
include/dt-bindings/clock/qcom,gcc-msm8916.h
include/dt-bindings/clock/qcom,gcc-msm8939.h
include/dt-bindings/reset/qcom,gcc-msm8916.h
include/dt-bindings/reset/qcom,gcc-msm8939.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml 0 → 100644
View file @ 0e2c9884
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8974 (including Pro) and MSM8226
Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8974 (all variants) and MSM8226.
See also::
include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
$ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,gcc-msm8226
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
- qcom,gcc-msm8974pro-ac
clocks:
items:
- description: XO source
- description: Sleep clock source
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@fc400000 {
compatible = "qcom,gcc-msm8974";
reg = <0x00100000 0x94000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "xo", "sleep_clk";
clocks = <&xo_board>,
<&sleep_clk>;
};
...
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
title: Qualcomm Global Clock & Reset Controller on MSM8976
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8976.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8976.
See also:
- dt-bindings/clock/qcom,gcc-msm8976.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8994
title: Qualcomm Global Clock & Reset Controller on MSM8994
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8994 and MSM8992.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8994 and MSM8992.
See also:
- dt-bindings/clock/qcom,gcc-msm8994.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
title: Qualcomm Global Clock & Reset Controller on MSM8996
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
Qualcomm global clock control module which provides the clocks, resets and
power domains on MSM8996.
See also:
- dt-bindings/clock/qcom,gcc-msm8996.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for MSM8998
title: Qualcomm Global Clock & Reset Controller on MSM8998
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on MSM8998.
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8998.
See also:
- dt-bindings/clock/qcom,gcc-msm8998.h
See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
View file @ 0e2c9884
......@@ -4,30 +4,27 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding
title: Qualcomm Global Clock & Reset Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains.
See also:
- dt-bindings/clock/qcom,gcc-ipq4019.h
- dt-bindings/clock/qcom,gcc-ipq6018.h
- dt-bindings/reset/qcom,gcc-ipq6018.h
- dt-bindings/clock/qcom,gcc-msm8953.h
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/clock/qcom,gcc-mdm9607.h
- dt-bindings/clock/qcom,gcc-mdm9615.h
- dt-bindings/reset/qcom,gcc-mdm9615.h
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
Qualcomm global clock control module provides the clocks, resets and power
domains.
See also::
include/dt-bindings/clock/qcom,gcc-ipq4019.h
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
include/dt-bindings/clock/qcom,gcc-mdm9607.h
include/dt-bindings/clock/qcom,gcc-mdm9615.h
include/dt-bindings/reset/qcom,gcc-mdm9615.h
allOf:
- $ref: "qcom,gcc.yaml#"
- $ref: qcom,gcc.yaml#
properties:
compatible:
......@@ -35,14 +32,8 @@ properties:
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8226
- qcom,gcc-msm8953
- qcom,gcc-msm8974
- qcom,gcc-msm8974pro
- qcom,gcc-msm8974pro-ac
- qcom,gcc-mdm9615
- qcom,gcc-sdm630
- qcom,gcc-sdm660
required:
- compatible
......@@ -50,10 +41,9 @@ required:
unevaluatedProperties: false
examples:
# Example for GCC for MSM8974:
- |
clock-controller@900000 {
compatible = "qcom,gcc-msm8974";
compatible = "qcom,gcc-mdm9607";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
......
Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcm2290.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for QCM2290
title: Qualcomm Global Clock & Reset Controller on QCM2290
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets
and power domains on QCM2290.
Qualcomm global clock control module provides the clocks, resets and power
domains on QCM2290.
See also:
- dt-bindings/clock/qcom,gcc-qcm2290.h
See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Bindingfor QCS404
title: Qualcomm Global Clock & Reset Controller on QCS404
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on QCS404.
Qualcomm global clock control module provides the clocks, resets and power
domains on QCS404.
See also:
- dt-bindings/clock/qcom,gcc-qcs404.h
See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC7180
title: Qualcomm Global Clock & Reset Controller on SC7180
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SC7180.
Qualcomm global clock control module provides the clocks, resets and power
domains on SC7180.
See also:
- dt-bindings/clock/qcom,gcc-sc7180.h
See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC7280
title: Qualcomm Global Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SC7280.
Qualcomm global clock control module provides the clocks, resets and power
domains on SC7280.
See also:
- dt-bindings/clock/qcom,gcc-sc7280.h
See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC8180x
title: Qualcomm Global Clock & Reset Controller on SC8180x
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SC8180x.
Qualcomm global clock control module provides the clocks, resets and power
domains on SC8180x.
See also:
- dt-bindings/clock/qcom,gcc-sc8180x.h
See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
title: Qualcomm Global Clock & Reset Controller on SC8280xp
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
Qualcomm global clock control module provides the clocks, resets and
power domains on SC8280xp.
See also:
- include/dt-bindings/clock/qcom,gcc-sc8280xp.h
See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml 0 → 100644
View file @ 0e2c9884
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM660/SDM630/SDM636 Global Clock & Reset Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDM630, SDM636 and SDM660
See also::
include/dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
$ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,gcc-sdm630
- qcom,gcc-sdm660
clocks:
items:
- description: XO source
- description: Sleep clock source
clock-names:
items:
- const: xo
- const: sleep_clk
power-domains:
maxItems: 1
required:
- compatible
unevaluatedProperties: false
examples:
# Example for GCC for SDM660:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sdm660";
reg = <0x00100000 0x94000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clock-names = "xo", "sleep_clk";
clocks = <&xo_board>,
<&sleep_clk>;
};
...
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding
title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SDM845
Qualcomm global clock control module provides the clocks, resets and power
domains on SDM670 and SDM845
See also:
- dt-bindings/clock/qcom,gcc-sdm845.h
See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SDX55
title: Qualcomm Global Clock & Reset Controller on SDX55
maintainers:
- Vinod Koul <vkoul@kernel.org>
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
Qualcomm global clock control module provides the clocks, resets and
power domains on SDX55
See also:
- dt-bindings/clock/qcom,gcc-sdx55.h
See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SDX65
title: Qualcomm Global Clock & Reset Controller on SDX65
maintainers:
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SDX65
Qualcomm global clock control module provides the clocks, resets and power
domains on SDX65
See also:
- dt-bindings/clock/qcom,gcc-sdx65.h
See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6115.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6115 and SM4250
title: Qualcomm Global Clock & Reset Controller on SM6115 and SM4250
maintainers:
- Iskren Chernev <iskren.chernev@gmail.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM4250/6115.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM4250/6115.
See also:
- dt-bindings/clock/qcom,gcc-sm6115.h
See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6125
title: Qualcomm Global Clock & Reset Controller on SM6125
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM6125.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6125.
See also:
- dt-bindings/clock/qcom,gcc-sm6125.h
See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6350
title: Qualcomm Global Clock & Reset Controller on SM6350
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM6350.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6350.
See also:
- dt-bindings/clock/qcom,gcc-sm6350.h
See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8150
title: Qualcomm Global Clock & Reset Controller on SM8150
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8150.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8150.
See also:
- dt-bindings/clock/qcom,gcc-sm8150.h
See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
View file @ 0e2c9884
......@@ -4,18 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8250
title: Qualcomm Global Clock & Reset Controller on SM8250
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8250.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8250.
See also:
- dt-bindings/clock/qcom,gcc-sm8250.h
See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8350
title: Qualcomm Global Clock & Reset Controller on SM8350
maintainers:
- Vinod Koul <vkoul@kernel.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8350.
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8350.
See also:
- dt-bindings/clock/qcom,gcc-sm8350.h
See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM8450
title: Qualcomm Global Clock & Reset Controller on SM8450
maintainers:
- Vinod Koul <vkoul@kernel.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM8450
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8450
See also:
- dt-bindings/clock/qcom,gcc-sm8450.h
See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gcc.yaml
View file @ 0e2c9884
......@@ -4,15 +4,15 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
title: Qualcomm Global Clock & Reset Controller Common Bindings
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
description: |
Common bindings for Qualcomm global clock control module which supports
the clocks, resets and power domains.
Common bindings for Qualcomm global clock control module providing the
clocks, resets and power domains.
properties:
'#clock-cells':
......
Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml
View file @ 0e2c9884
......@@ -4,13 +4,13 @@
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660
title: Qualcomm Graphics Clock & Reset Controller on SDM630 and SDM660
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
Qualcomm graphics clock control module provides the clocks, resets and
power domains on SDM630 and SDM660.
See also dt-bindings/clock/qcom,gpucc-sdm660.h.
......
Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding
title: Qualcomm Graphics Clock & Reset Controller on SM8350
maintainers:
- Robert Foss <robert.foss@linaro.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
power domains on Qualcomm SoCs.
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also:
dt-bindings/clock/qcom,gpucc-sm8350.h
See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
View file @ 0e2c9884
......@@ -4,23 +4,23 @@
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding
title: Qualcomm Graphics Clock & Reset Controller
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
power domains on Qualcomm SoCs.
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also:
dt-bindings/clock/qcom,gpucc-sdm845.h
dt-bindings/clock/qcom,gpucc-sc7180.h
dt-bindings/clock/qcom,gpucc-sc7280.h
dt-bindings/clock/qcom,gpucc-sc8280xp.h
dt-bindings/clock/qcom,gpucc-sm6350.h
dt-bindings/clock/qcom,gpucc-sm8150.h
dt-bindings/clock/qcom,gpucc-sm8250.h
See also::
include/dt-bindings/clock/qcom,gpucc-sdm845.h
include/dt-bindings/clock/qcom,gpucc-sc7180.h
include/dt-bindings/clock/qcom,gpucc-sc7280.h
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
include/dt-bindings/clock/qcom,gpucc-sm6350.h
include/dt-bindings/clock/qcom,gpucc-sm8150.h
include/dt-bindings/clock/qcom,gpucc-sm8250.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,lcc.txt deleted 100644 → 0
View file @ e0a1d139
Qualcomm LPASS Clock & Reset Controller Binding
------------------------------------------------
Required properties :
- compatible : shall contain only one of the following:
"qcom,lcc-msm8960"
"qcom,lcc-apq8064"
"qcom,lcc-ipq8064"
"qcom,lcc-mdm9615"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1
- #reset-cells : shall contain 1
Example:
clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/clock/qcom,lcc.yaml 0 → 100644
View file @ 0e2c9884
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,lcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Clock & Reset Controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
enum:
- qcom,lcc-apq8064
- qcom,lcc-ipq8064
- qcom,lcc-mdm9615
- qcom,lcc-msm8960
clocks:
maxItems: 8
clock-names:
maxItems: 8
'#clock-cells':
const: 1
'#reset-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,lcc-apq8064
- qcom,lcc-msm8960
then:
properties:
clocks:
items:
- description: Board PXO source
- description: PLL 4 Vote clock
- description: MI2S codec clock
- description: Mic I2S codec clock
- description: Mic I2S spare clock
- description: Speaker I2S codec clock
- description: Speaker I2S spare clock
- description: PCM codec clock
clock-names:
items:
- const: pxo
- const: pll4_vote
- const: mi2s_codec_clk
- const: codec_i2s_mic_codec_clk
- const: spare_i2s_mic_codec_clk
- const: codec_i2s_spkr_codec_clk
- const: spare_i2s_spkr_codec_clk
- const: pcm_codec_clk
required:
- clocks
- clock-names
examples:
- |
clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/clock/qcom,lpasscc.txt deleted 100644 → 0
View file @ e0a1d139
Qualcomm LPASS Clock Controller Binding
-----------------------------------------------
Required properties :
- compatible : shall contain "qcom,sdm845-lpasscc"
- #clock-cells : from common clock binding, shall contain 1.
- reg : shall contain base register address and size,
in the order
Index-0 maps to LPASS_CC register region
Index-1 maps to LPASS_QDSP6SS register region
Optional properties :
- reg-names : register names of LPASS domain
"cc", "qdsp6ss".
Example:
The below node has to be defined in the cases where the LPASS peripheral loader
would bring the subsystem out of reset.
lpasscc: clock-controller@17014000 {
compatible = "qcom,sdm845-lpasscc";
reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
reg-names = "cc", "qdsp6ss";
#clock-cells = <1>;
};
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
View file @ 0e2c9884
......@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Multimedia Clock & Reset Controller Binding
title: Qualcomm Multimedia Clock & Reset Controller
maintainers:
- Jeffrey Hugo <quic_jhugo@quicinc.com>
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm multimedia clock control module which supports the clocks, resets and
Qualcomm multimedia clock control module provides the clocks, resets and
power domains.
properties:
......@@ -99,6 +99,44 @@ allOf:
- const: dsi2pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-msm8974
then:
properties:
clocks:
items:
- description: Board XO source
- description: MMSS GPLL0 voted clock
- description: GPLL0 voted clock
- description: GPLL1 voted clock
- description: GFX3D clock source
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
- description: DSI phy instance 1 dsi clock
- description: DSI phy instance 1 byte clock
- description: HDMI phy PLL clock
- description: eDP phy PLL link clock
- description: eDP phy PLL vco clock
clock-names:
items:
- const: xo
- const: mmss_gpll0_vote
- const: gpll0_vote
- const: gpll1_vote
- const: gfx3d_clk_src
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
- const: hdmipll
- const: edp_link_clk
- const: edp_vco_div
- if:
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
title: Qualcomm Graphics Clock & Reset Controller on MSM8998
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm graphics clock control module which supports the clocks, resets and
power domains on MSM8998.
Qualcomm graphics clock control module provides the clocks, resets and power
domains on MSM8998.
See also dt-bindings/clock/qcom,gpucc-msm8998.h.
See also:: include/dt-bindings/clock/qcom,gpucc-msm8998.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,q6sstopcc.yaml
View file @ 0e2c9884
......@@ -11,7 +11,7 @@ maintainers:
properties:
compatible:
const: "qcom,qcs404-q6sstopcc"
const: qcom,qcs404-q6sstopcc
reg:
items:
......
Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
title: Qualcomm Display Clock & Reset Controller on QCM2290
maintainers:
- Loic Poulain <loic.poulain@linaro.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on qcm2290.
Qualcomm display clock control module provides the clocks, resets and power
domains on qcm2290.
See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View file @ 0e2c9884
......@@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- qcom,qdu1000-rpmh-clk
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
......
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SC7180
title: Qualcomm Camera Clock & Reset Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SC7180.
Qualcomm camera clock control module provides the clocks, resets and power
domains on SC7180.
See also:
- dt-bindings/clock/qcom,camcc-sc7180.h
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SC7180
title: Qualcomm Display Clock & Reset Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SC7180.
Qualcomm display clock control module provides the clocks, resets and power
domains on SC7180.
See also dt-bindings/clock/qcom,dispcc-sc7180.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller Binding for SC7180
title: Qualcomm LPASS Core Clock Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core clock control module which supports the clocks and
power domains on SC7180.
Qualcomm LPASS core clock control module provides the clocks and power
domains on SC7180.
See also:
- dt-bindings/clock/qcom,lpasscorecc-sc7180.h
See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sc7180-mss.yaml
View file @ 0e2c9884
......@@ -4,16 +4,15 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Modem Clock Controller Binding for SC7180
title: Qualcomm Modem Clock Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm modem clock control module which supports the clocks on SC7180.
Qualcomm modem clock control module provides the clocks on SC7180.
See also:
- dt-bindings/clock/qcom,mss-sc7180.h
See also:: include/dt-bindings/clock/qcom,mss-sc7180.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sc7280-camcc.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SC7280
title: Qualcomm Camera Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
Qualcomm camera clock control module provides the clocks, resets and
power domains on SC7280.
See also dt-bindings/clock/qcom,camcc-sc7280.h
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SC7280
title: Qualcomm Display Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SC7280.
Qualcomm display clock control module provides the clocks, resets and power
domains on SC7280.
See also dt-bindings/clock/qcom,dispcc-sc7280.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller Binding for SC7280
title: Qualcomm LPASS Core Clock Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core clock control module which supports the clocks and
power domains on SC7280.
Qualcomm LPASS core clock control module provides the clocks and power
domains on SC7280.
See also:
- dt-bindings/clock/qcom,lpass-sc7280.h
See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
View file @ 0e2c9884
......@@ -4,18 +4,18 @@
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
title: Qualcomm LPASS Core & Audio Clock Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm LPASS core and audio clock control module which supports the
clocks and power domains on SC7280.
Qualcomm LPASS core and audio clock control module provides the clocks and
power domains on SC7280.
See also:
- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
See also::
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
properties:
clocks: true
......
Documentation/devicetree/bindings/clock/qcom,sdm845-camcc.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sdm845-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SDM845
title: Qualcomm Camera Clock & Reset Controller on SDM845
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SDM845.
Qualcomm camera clock control module provides the clocks, resets and power
domains on SDM845.
See also dt-bindings/clock/qcom,camcc-sm845.h
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller Binding for SDM845
title: Qualcomm Display Clock & Reset Controller on SDM845
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SDM845.
Qualcomm display clock control module provides the clocks, resets and power
domains on SDM845.
See also dt-bindings/clock/qcom,dispcc-sdm845.h.
See also:: include/dt-bindings/clock/qcom,dispcc-sdm845.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sdm845-lpasscc.yaml 0 → 100644
View file @ 0e2c9884
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdm845-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM845 LPASS Clock Controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm SDM845 LPASS (Low Power Audio SubSystem) Clock Controller.
See also:: include/dt-bindings/clock/qcom,lpass-sdm845.h
properties:
compatible:
const: qcom,sdm845-lpasscc
'#clock-cells':
const: 1
reg:
maxItems: 2
reg-names:
items:
- const: cc
- const: qdsp6ss
required:
- compatible
- '#clock-cells'
- reg
- reg-names
additionalProperties: false
examples:
- |
clock-controller@17014000 {
compatible = "qcom,sdm845-lpasscc";
reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
reg-names = "cc", "qdsp6ss";
#clock-cells = <1>;
};
Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml
View file @ 0e2c9884
......@@ -10,11 +10,10 @@ maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm display clock control module which supports the clocks and
power domains on SM6115.
Qualcomm display clock control module provides the clocks and power domains
on SM6115.
See also:
include/dt-bindings/clock/qcom,sm6115-dispcc.h
See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sm6375-dispcc.yaml 0 → 100644
View file @ 0e2c9884
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SM6375
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM6375.
See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,sm6375-dispcc
clocks:
items:
- description: Board XO source
- description: GPLL0 source from GCC
- description: Byte clock from DSI PHY
- description: Pixel clock from DSI PHY
required:
- compatible
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@5f00000 {
compatible = "qcom,sm6375-dispcc";
reg = <0x05f00000 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy 0>,
<&dsi_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml
View file @ 0e2c9884
......@@ -4,17 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SM6375
title: Qualcomm Global Clock & Reset Controller on SM6375
maintainers:
- Konrad Dybcio <konrad.dybcio@somainline.org>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SM6375
Qualcomm global clock control module provides the clocks, resets and power
domains on SM6375
See also:
- dt-bindings/clock/qcom,sm6375-gcc.h
See also:: include/dt-bindings/clock/qcom,sm6375-gcc.h
allOf:
- $ref: qcom,gcc.yaml#
......
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View file @ 0e2c9884
......@@ -4,16 +4,16 @@
$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller Binding for SM8450
title: Qualcomm Camera Clock & Reset Controller on SM8450
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
description: |
Qualcomm camera clock control module which supports the clocks, resets and
power domains on SM8450.
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
See also include/dt-bindings/clock/qcom,sm8450-camcc.h
See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
View file @ 0e2c9884
......@@ -10,11 +10,10 @@ maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains on SM8450.
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,sm8450-dispcc.h
See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
properties:
compatible:
......
Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml 0 → 100644
View file @ 0e2c9884
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SM8550
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8550
See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
properties:
compatible:
const: qcom,sm8550-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE 0 Pipe clock source
- description: PCIE 1 Pipe clock source
- description: PCIE 1 Phy Auxiliary clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,sm8550-gcc";
reg = <0x00100000 0x001f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&pcie0_phy>,
<&pcie1_phy>,
<&pcie_1_phy_aux_clk>,
<&ufs_mem_phy 0>,
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
View file @ 0e2c9884
......@@ -4,21 +4,21 @@
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller Binding
title: Qualcomm Video Clock & Reset Controller
maintainers:
- Taniya Das <tdas@codeaurora.org>
description: |
Qualcomm video clock control module which supports the clocks, resets and
power domains on Qualcomm SoCs.
See also:
dt-bindings/clock/qcom,videocc-sc7180.h
dt-bindings/clock/qcom,videocc-sc7280.h
dt-bindings/clock/qcom,videocc-sdm845.h
dt-bindings/clock/qcom,videocc-sm8150.h
dt-bindings/clock/qcom,videocc-sm8250.h
Qualcomm video clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,videocc-sc7180.h
include/dt-bindings/clock/qcom,videocc-sc7280.h
include/dt-bindings/clock/qcom,videocc-sdm845.h
include/dt-bindings/clock/qcom,videocc-sm8150.h
include/dt-bindings/clock/qcom,videocc-sm8250.h
properties:
compatible:
......
drivers/clk/clk.c
View file @ 0e2c9884
......@@ -603,10 +603,15 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
}
clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
trace_clk_rate_request_start(&parent_req);
ret = clk_core_round_rate_nolock(parent, &parent_req);
if (ret)
return ret;
trace_clk_rate_request_done(&parent_req);
best = parent_req.rate;
} else if (parent) {
best = clk_core_get_rate_nolock(parent);
......@@ -630,10 +635,15 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
struct clk_rate_request parent_req;
clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
trace_clk_rate_request_start(&parent_req);
ret = clk_core_round_rate_nolock(parent, &parent_req);
if (ret)
continue;
trace_clk_rate_request_done(&parent_req);
parent_rate = parent_req.rate;
} else {
parent_rate = clk_core_get_rate_nolock(parent);
......@@ -1468,6 +1478,7 @@ static void clk_core_init_rate_req(struct clk_core * const core,
if (!core)
return;
req->core = core;
req->rate = rate;
clk_core_get_boundaries(core, &req->min_rate, &req->max_rate);
......@@ -1550,10 +1561,15 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
struct clk_rate_request parent_req;
clk_core_forward_rate_req(core, req, core->parent, &parent_req, req->rate);
trace_clk_rate_request_start(&parent_req);
ret = clk_core_round_rate_nolock(core->parent, &parent_req);
if (ret)
return ret;
trace_clk_rate_request_done(&parent_req);
req->best_parent_rate = parent_req.rate;
req->rate = parent_req.rate;
......@@ -1604,10 +1620,14 @@ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
clk_core_init_rate_req(hw->core, &req, rate);
trace_clk_rate_request_start(&req);
ret = clk_core_round_rate_nolock(hw->core, &req);
if (ret)
return 0;
trace_clk_rate_request_done(&req);
return req.rate;
}
EXPORT_SYMBOL_GPL(clk_hw_round_rate);
......@@ -1636,8 +1656,12 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
clk_core_init_rate_req(clk->core, &req, rate);
trace_clk_rate_request_start(&req);
ret = clk_core_round_rate_nolock(clk->core, &req);
trace_clk_rate_request_done(&req);
if (clk->exclusive_count)
clk_core_rate_protect(clk->core);
......@@ -2129,10 +2153,14 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core,
clk_core_init_rate_req(core, &req, rate);
trace_clk_rate_request_start(&req);
ret = clk_core_determine_round_nolock(core, &req);
if (ret < 0)
return NULL;
trace_clk_rate_request_done(&req);
best_parent_rate = req.best_parent_rate;
new_rate = req.rate;
parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
......@@ -2328,8 +2356,12 @@ static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core,
clk_core_init_rate_req(core, &req, req_rate);
trace_clk_rate_request_start(&req);
ret = clk_core_round_rate_nolock(core, &req);
trace_clk_rate_request_done(&req);
/* restore the protection */
clk_core_rate_restore_protect(core, cnt);
......
drivers/clk/mediatek/Kconfig
View file @ 0e2c9884
......@@ -11,6 +11,13 @@ config COMMON_CLK_MEDIATEK
help
MediaTek SoCs' clock support.
config COMMON_CLK_MEDIATEK_FHCTL
bool "clock driver for MediaTek FHCTL hardware control"
select COMMON_CLK_MEDIATEK
help
This driver supports MediaTek frequency hopping and
spread spectrum clocking features.
config COMMON_CLK_MT2701
bool "Clock driver for MediaTek MT2701"
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
......@@ -553,6 +560,7 @@ config COMMON_CLK_MT8186
bool "Clock driver for MediaTek MT8186"
depends on ARM64 || COMPILE_TEST
select COMMON_CLK_MEDIATEK
select COMMON_CLK_MEDIATEK_FHCTL
default ARCH_MEDIATEK
help
This driver supports MediaTek MT8186 clocks.
......
drivers/clk/mediatek/Makefile
View file @ 0e2c9884
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
......
drivers/clk/mediatek/clk-fhctl.c 0 → 100644
View file @ 0e2c9884
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
*/
#include <linux/io.h>
#include <linux/iopoll.h>
#include "clk-mtk.h"
#include "clk-pllfh.h"
#include "clk-fhctl.h"
#define PERCENT_TO_DDSLMT(dds, percent_m10) \
((((dds) * (percent_m10)) >> 5) / 100)
static const struct fhctl_offset fhctl_offset = {
.offset_hp_en = 0x0,
.offset_clk_con = 0x8,
.offset_rst_con = 0xc,
.offset_slope0 = 0x10,
.offset_slope1 = 0x14,
.offset_cfg = 0x0,
.offset_updnlmt = 0x4,
.offset_dds = 0x8,
.offset_dvfs = 0xc,
.offset_mon = 0x10,
};
const struct fhctl_offset *fhctl_get_offset_table(void)
{
return &fhctl_offset;
}
static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
const struct fh_pll_data *data)
{
pr_info("hp_en<%x>,clk_con<%x>,slope0<%x>,slope1<%x>\n",
readl(regs->reg_hp_en), readl(regs->reg_clk_con),
readl(regs->reg_slope0), readl(regs->reg_slope1));
pr_info("cfg<%x>,lmt<%x>,dds<%x>,dvfs<%x>,mon<%x>\n",
readl(regs->reg_cfg), readl(regs->reg_updnlmt),
readl(regs->reg_dds), readl(regs->reg_dvfs),
readl(regs->reg_mon));
pr_info("pcw<%x>\n", readl(pll->pcw_addr));
}
static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
const struct fh_pll_data *data, u32 rate)
{
u32 updnlmt_val, r;
writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
if (rate > 0) {
/* Set the relative parameter registers (dt/df/upbnd/downbnd) */
r = readl(regs->reg_cfg);
r &= ~(data->msk_frddsx_dys);
r |= (data->df_val << (ffs(data->msk_frddsx_dys) - 1));
writel(r, regs->reg_cfg);
r = readl(regs->reg_cfg);
r &= ~(data->msk_frddsx_dts);
r |= (data->dt_val << (ffs(data->msk_frddsx_dts) - 1));
writel(r, regs->reg_cfg);
writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
regs->reg_dds);
/* Calculate UPDNLMT */
updnlmt_val = PERCENT_TO_DDSLMT((readl(regs->reg_dds) &
data->dds_mask), rate) <<
data->updnlmt_shft;
writel(updnlmt_val, regs->reg_updnlmt);
writel(readl(regs->reg_hp_en) | BIT(data->fh_id),
regs->reg_hp_en);
/* Enable SSC */
writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);
/* Enable Hopping control */
writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
} else {
/* Switch to APMIXEDSYS control */
writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),
regs->reg_hp_en);
/* Wait for DDS to be stable */
udelay(30);
}
return 0;
}
static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
const struct fh_pll_data *data,
struct fh_pll_state *state, unsigned int new_dds)
{
u32 dds_mask = data->dds_mask;
u32 mon_dds = 0;
u32 con_pcw_tmp;
int ret;
if (state->ssc_rate)
fhctl_set_ssc_regs(pll, regs, data, 0);
writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
regs->reg_dds);
writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);
writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
writel(data->slope0_value, regs->reg_slope0);
writel(data->slope1_value, regs->reg_slope1);
writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);
writel((new_dds) | (data->dvfs_tri), regs->reg_dvfs);
/* Wait 1000 us until DDS stable */
ret = readl_poll_timeout_atomic(regs->reg_mon, mon_dds,
(mon_dds & dds_mask) == new_dds,
10, 1000);
if (ret) {
pr_warn("%s: FHCTL hopping timeout\n", pll->data->name);
dump_hw(pll, regs, data);
}
con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);
con_pcw_tmp = (con_pcw_tmp | (readl(regs->reg_mon) & dds_mask) |
data->pcwchg);
writel(con_pcw_tmp, pll->pcw_addr);
writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);
if (state->ssc_rate)
fhctl_set_ssc_regs(pll, regs, data, state->ssc_rate);
return ret;
}
static unsigned int __get_postdiv(struct mtk_clk_pll *pll)
{
unsigned int regval;
regval = readl(pll->pd_addr) >> pll->data->pd_shift;
regval &= POSTDIV_MASK;
return BIT(regval);
}
static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv)
{
unsigned int regval;
regval = readl(pll->pd_addr);
regval &= ~(POSTDIV_MASK << pll->data->pd_shift);
regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;
writel(regval, pll->pd_addr);
}
static int fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds,
unsigned int postdiv)
{
const struct fh_pll_data *data = &fh->pllfh_data->data;
struct fh_pll_state *state = &fh->pllfh_data->state;
struct fh_pll_regs *regs = &fh->regs;
struct mtk_clk_pll *pll = &fh->clk_pll;
spinlock_t *lock = fh->lock;
unsigned int pll_postdiv;
unsigned long flags = 0;
int ret;
if (postdiv) {
pll_postdiv = __get_postdiv(pll);
if (postdiv > pll_postdiv)
__set_postdiv(pll, postdiv);
}
spin_lock_irqsave(lock, flags);
ret = hopping_hw_flow(pll, regs, data, state, new_dds);
spin_unlock_irqrestore(lock, flags);
if (postdiv && postdiv < pll_postdiv)
__set_postdiv(pll, postdiv);
return ret;
}
static int fhctl_ssc_enable(struct mtk_fh *fh, u32 rate)
{
const struct fh_pll_data *data = &fh->pllfh_data->data;
struct fh_pll_state *state = &fh->pllfh_data->state;
struct fh_pll_regs *regs = &fh->regs;
struct mtk_clk_pll *pll = &fh->clk_pll;
spinlock_t *lock = fh->lock;
unsigned long flags = 0;
spin_lock_irqsave(lock, flags);
fhctl_set_ssc_regs(pll, regs, data, rate);
state->ssc_rate = rate;
spin_unlock_irqrestore(lock, flags);
return 0;
}
static const struct fh_operation fhctl_ops = {
.hopping = fhctl_hopping,
.ssc_enable = fhctl_ssc_enable,
};
const struct fh_operation *fhctl_get_ops(void)
{
return &fhctl_ops;
}
void fhctl_hw_init(struct mtk_fh *fh)
{
const struct fh_pll_data data = fh->pllfh_data->data;
struct fh_pll_state state = fh->pllfh_data->state;
struct fh_pll_regs regs = fh->regs;
u32 val;
/* initial hw register */
val = readl(regs.reg_clk_con) | BIT(data.fh_id);
writel(val, regs.reg_clk_con);
val = readl(regs.reg_rst_con) & ~BIT(data.fh_id);
writel(val, regs.reg_rst_con);
val = readl(regs.reg_rst_con) | BIT(data.fh_id);
writel(val, regs.reg_rst_con);
writel(0x0, regs.reg_cfg);
writel(0x0, regs.reg_updnlmt);
writel(0x0, regs.reg_dds);
/* enable ssc if needed */
if (state.ssc_rate)
fh->ops->ssc_enable(fh, state.ssc_rate);
}
drivers/clk/mediatek/clk-fhctl.h 0 → 100644
View file @ 0e2c9884
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
*/
#ifndef __CLK_FHCTL_H
#define __CLK_FHCTL_H
struct fhctl_offset {
u32 offset_hp_en;
u32 offset_clk_con;
u32 offset_rst_con;
u32 offset_slope0;
u32 offset_slope1;
u32 offset_cfg;
u32 offset_updnlmt;
u32 offset_dds;
u32 offset_dvfs;
u32 offset_mon;
};
const struct fhctl_offset *fhctl_get_offset_table(void);
const struct fh_operation *fhctl_get_ops(void);
void fhctl_hw_init(struct mtk_fh *fh);
#endif
drivers/clk/mediatek/clk-mt6795-topckgen.c
View file @ 0e2c9884
......@@ -359,19 +359,19 @@ static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_ARMCA53PLL_754M, "armca53pll_754m", "clk26m", 1, 2),
FACTOR(CLK_TOP_ARMCA53PLL_502M, "armca53pll_502m", "clk26m", 1, 3),
FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0),
FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
......@@ -402,20 +402,20 @@ static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0),
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
......@@ -423,21 +423,21 @@ static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0),
FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
......
drivers/clk/mediatek/clk-mt7986-infracfg.c
View file @ 0e2c9884
......@@ -153,7 +153,7 @@ static const struct mtk_gate infra_clks[] = {
18),
GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
19),
GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m_sel", 20),
GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),
GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
/* INFRA2 */
......
drivers/clk/mediatek/clk-mt8173.c
View file @ 0e2c9884
......@@ -37,19 +37,19 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
FACTOR_FLAGS(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7, 0),
FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
FACTOR_FLAGS(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26, 0),
FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
......@@ -84,20 +84,20 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4, 0),
FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
......@@ -105,21 +105,21 @@ static const struct mtk_fixed_factor top_divs[] __initconst = {
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2, 0),
FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
......
drivers/clk/mediatek/clk-mt8183.c
View file @ 0e2c9884
......@@ -31,150 +31,78 @@ static const struct mtk_fixed_factor top_early_divs[] = {
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
2),
FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
1),
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
2),
FACTOR(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1,
2),
FACTOR(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1,
4),
FACTOR(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1,
8),
FACTOR(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1,
16),
FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1,
3),
FACTOR(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1,
2),
FACTOR(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1,
4),
FACTOR(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1,
8),
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1,
5),
FACTOR(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1,
2),
FACTOR(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1,
4),
FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1,
7),
FACTOR(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1,
2),
FACTOR(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1,
4),
FACTOR(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1,
1),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
2),
FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1,
2),
FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1,
4),
FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1,
8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1,
3),
FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1,
2),
FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1,
4),
FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1,
8),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1,
5),
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1,
2),
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1,
4),
FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1,
8),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1,
7),
FACTOR(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1,
1),
FACTOR(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1,
2),
FACTOR(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1,
4),
FACTOR(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1,
8),
FACTOR(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1,
16),
FACTOR(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1,
32),
FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1,
1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1,
2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1,
4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1,
8),
FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1,
1),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1,
2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1,
4),
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1,
8),
FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1,
1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1,
4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1,
8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1,
16),
FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1,
1),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1,
4),
FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1,
2),
FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1,
4),
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1,
5),
FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1,
2),
FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1,
4),
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1,
6),
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1,
7),
FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1,
1),
FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1,
1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1,
2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1,
4),
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1,
8),
FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1,
16),
FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1,
1),
FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1,
2),
FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1,
4),
FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1,
8),
FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1,
16),
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1,
2),
FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1,
16),
FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
FACTOR_FLAGS(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D2, "syspll_d2_d2", "syspll_d2", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D4, "syspll_d2_d4", "syspll_d2", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D8, "syspll_d2_d8", "syspll_d2", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D2_D16, "syspll_d2_d16", "syspll_d2", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D2, "syspll_d3_d2", "syspll_d3", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D4, "syspll_d3_d4", "syspll_d3", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D3_D8, "syspll_d3_d8", "syspll_d3", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D2, "syspll_d5_d2", "syspll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D5_D4, "syspll_d5_d4", "syspll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D2, "syspll_d7_d2", "syspll_d7", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_SYSPLL_D7_D4, "syspll_d7_d4", "syspll_d7", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_CK, "univpll_ck", "univpll", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_CK, "univ_192m_ck", "univpll_192m", 1, 1, 0),
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D2, "univ_192m_d2", "univ_192m_ck", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D4, "univ_192m_d4", "univ_192m_ck", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D8, "univ_192m_d8", "univ_192m_ck", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D16, "univ_192m_d16", "univ_192m_ck", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVP_192M_D32, "univ_192m_d32", "univ_192m_ck", 1, 32, 0),
FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16, 0),
};
static const char * const axi_parents[] = {
......
drivers/clk/mediatek/clk-mt8186-apmixedsys.c
View file @ 0e2c9884
......@@ -9,6 +9,7 @@
#include "clk-mtk.h"
#include "clk-pll.h"
#include "clk-pllfh.h"
#define MT8186_PLL_FMAX (3800UL * MHZ)
#define MT8186_PLL_FMIN (1500UL * MHZ)
......@@ -76,6 +77,59 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
};
enum fh_pll_id {
FH_ARMPLL_LL,
FH_ARMPLL_BL,
FH_CCIPLL,
FH_MAINPLL,
FH_MMPLL,
FH_TVDPLL,
FH_RESERVE6,
FH_ADSPPLL,
FH_MFGPLL,
FH_NNAPLL,
FH_NNA2PLL,
FH_MSDCPLL,
FH_RESERVE12,
FH_NR_FH,
};
#define FH(_pllid, _fhid, _offset) { \
.data = { \
.pll_id = _pllid, \
.fh_id = _fhid, \
.fhx_offset = _offset, \
.dds_mask = GENMASK(21, 0), \
.slope0_value = 0x6003c97, \
.slope1_value = 0x6003c97, \
.sfstrx_en = BIT(2), \
.frddsx_en = BIT(1), \
.fhctlx_en = BIT(0), \
.tgl_org = BIT(31), \
.dvfs_tri = BIT(31), \
.pcwchg = BIT(31), \
.dt_val = 0x0, \
.df_val = 0x9, \
.updnlmt_shft = 16, \
.msk_frddsx_dys = GENMASK(23, 20), \
.msk_frddsx_dts = GENMASK(19, 16), \
}, \
}
static struct mtk_pllfh_data pllfhs[] = {
FH(CLK_APMIXED_ARMPLL_LL, FH_ARMPLL_LL, 0x003C),
FH(CLK_APMIXED_ARMPLL_BL, FH_ARMPLL_BL, 0x0050),
FH(CLK_APMIXED_CCIPLL, FH_CCIPLL, 0x0064),
FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078),
FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C),
FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x00A0),
FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x00C8),
FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0x00DC),
FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x00F0),
FH(CLK_APMIXED_NNA2PLL, FH_NNA2PLL, 0x0104),
FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),
};
static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
{ .compatible = "mediatek,mt8186-apmixedsys", },
{}
......@@ -85,13 +139,17 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
const u8 *fhctl_node = "mediatek,mt8186-fhctl";
int r;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;
......@@ -104,7 +162,8 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
return r;
unregister_plls:
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
free_apmixed_data:
mtk_free_clk_data(clk_data);
return r;
......@@ -116,7 +175,8 @@ static int clk_mt8186_apmixed_remove(struct platform_device *pdev)
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
mtk_free_clk_data(clk_data);
return 0;
......
drivers/clk/mediatek/clk-mt8186-mfg.c
View file @ 0e2c9884
......@@ -16,8 +16,9 @@ static const struct mtk_gate_regs mfg_cg_regs = {
.sta_ofs = 0x0,
};
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
#define GATE_MFG(_id, _name, _parent, _shift) \
GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \
&mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT)
static const struct mtk_gate mfg_clks[] = {
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg", 0),
......
drivers/clk/mediatek/clk-mt8186-topckgen.c
View file @ 0e2c9884
......@@ -19,37 +19,37 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3_D32, "univpll_d3_d32", "univpll_d3", 1, 32),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univ2pll", 1, 13),
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3_D32, "univpll_d3_d32", "univpll_d3", 1, 32, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univ2pll", 1, 13, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
......@@ -689,6 +689,28 @@ static const struct of_device_id of_match_clk_mt8186_topck[] = {
{}
};
/* Register mux notifier for MFG mux */
static int clk_mt8186_reg_mfg_mux_notifier(struct device *dev, struct clk *clk)
{
struct mtk_mux_nb *mfg_mux_nb;
int i;
mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
if (!mfg_mux_nb)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(top_mtk_muxes); i++)
if (top_mtk_muxes[i].id == CLK_TOP_MFG)
break;
if (i == ARRAY_SIZE(top_mtk_muxes))
return -EINVAL;
mfg_mux_nb->ops = top_mtk_muxes[i].ops;
mfg_mux_nb->bypass_index = 0; /* Bypass to 26M crystal */
return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
}
static int clk_mt8186_topck_probe(struct platform_device *pdev)
{
struct clk_hw_onecell_data *clk_data;
......@@ -730,6 +752,11 @@ static int clk_mt8186_topck_probe(struct platform_device *pdev)
if (r)
goto unregister_composite_muxes;
r = clk_mt8186_reg_mfg_mux_notifier(&pdev->dev,
clk_data->hws[CLK_TOP_MFG]->clk);
if (r)
goto unregister_composite_divs;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_composite_divs;
......
drivers/clk/mediatek/clk-mt8192.c
View file @ 0e2c9884
......@@ -31,38 +31,38 @@ static const struct mtk_fixed_factor top_early_divs[] = {
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16),
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D16, "mainpll_d4_d16", "mainpll_d4", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
......@@ -96,12 +96,12 @@ static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 1, 16),
FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
FACTOR(CLK_TOP_ADSPPLL, "adsppll_ck", "adsppll", 1, 1),
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll_192m", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
};
static const char * const axi_parents[] = {
......
drivers/clk/mediatek/clk-mt8195-topckgen.c
View file @ 0e2c9884
......@@ -35,45 +35,45 @@ static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
......
drivers/clk/mediatek/clk-mtk.c
View file @ 0e2c9884
......@@ -149,7 +149,7 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
}
hw = clk_hw_register_fixed_factor(NULL, ff->name, ff->parent_name,
CLK_SET_RATE_PARENT, ff->mult, ff->div);
ff->flags, ff->mult, ff->div);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", ff->name,
......
drivers/clk/mediatek/clk-mtk.h
View file @ 0e2c9884
......@@ -47,16 +47,21 @@ struct mtk_fixed_factor {
const char *parent_name;
int mult;
int div;
unsigned long flags;
};
#define FACTOR(_id, _name, _parent, _mult, _div) { \
#define FACTOR_FLAGS(_id, _name, _parent, _mult, _div, _fl) { \
.id = _id, \
.name = _name, \
.parent_name = _parent, \
.mult = _mult, \
.div = _div, \
.flags = _fl, \
}
#define FACTOR(_id, _name, _parent, _mult, _div) \
FACTOR_FLAGS(_id, _name, _parent, _mult, _div, CLK_SET_RATE_PARENT)
int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num,
......
drivers/clk/mediatek/clk-pll.c
View file @ 0e2c9884
......@@ -27,37 +27,10 @@
#define AUDPLL_TUNER_EN BIT(31)
#define POSTDIV_MASK 0x7
/* default 7 bits integer, can be overridden with pcwibits. */
#define INTEGER_BITS 7
/*
* MediaTek PLLs are configured through their pcw value. The pcw value describes
* a divider in the PLL feedback loop which consists of 7 bits for the integer
* part and the remaining bits (if present) for the fractional part. Also they
* have a 3 bit power-of-two post divider.
*/
struct mtk_clk_pll {
struct clk_hw hw;
void __iomem *base_addr;
void __iomem *pd_addr;
void __iomem *pwr_addr;
void __iomem *tuner_addr;
void __iomem *tuner_en_addr;
void __iomem *pcw_addr;
void __iomem *pcw_chg_addr;
void __iomem *en_addr;
const struct mtk_pll_data *data;
};
static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
{
return container_of(hw, struct mtk_clk_pll, hw);
}
static int mtk_pll_is_prepared(struct clk_hw *hw)
int mtk_pll_is_prepared(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
......@@ -161,8 +134,8 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
* @fin: The input frequency
*
*/
static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
u32 freq, u32 fin)
void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
u32 freq, u32 fin)
{
unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
const struct mtk_pll_div_table *div_table = pll->data->div_table;
......@@ -198,8 +171,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
*pcw = (u32)_pcw;
}
static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 pcw = 0;
......@@ -211,8 +184,7 @@ static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 postdiv;
......@@ -227,8 +199,8 @@ static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
}
static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 pcw = 0;
......@@ -239,7 +211,7 @@ static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
}
static int mtk_pll_prepare(struct clk_hw *hw)
int mtk_pll_prepare(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r;
......@@ -273,7 +245,7 @@ static int mtk_pll_prepare(struct clk_hw *hw)
return 0;
}
static void mtk_pll_unprepare(struct clk_hw *hw)
void mtk_pll_unprepare(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r;
......@@ -301,7 +273,7 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
writel(r, pll->pwr_addr);
}
static const struct clk_ops mtk_pll_ops = {
const struct clk_ops mtk_pll_ops = {
.is_prepared = mtk_pll_is_prepared,
.prepare = mtk_pll_prepare,
.unprepare = mtk_pll_unprepare,
......@@ -310,18 +282,15 @@ static const struct clk_ops mtk_pll_ops = {
.set_rate = mtk_pll_set_rate,
};
static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
void __iomem *base)
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
const struct mtk_pll_data *data,
void __iomem *base,
const struct clk_ops *pll_ops)
{
struct mtk_clk_pll *pll;
struct clk_init_data init = {};
int ret;
const char *parent_name = "clk26m";
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return ERR_PTR(-ENOMEM);
pll->base_addr = base + data->reg;
pll->pwr_addr = base + data->pwr_reg;
pll->pd_addr = base + data->pd_reg;
......@@ -343,7 +312,7 @@ static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
init.name = data->name;
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
init.ops = &mtk_pll_ops;
init.ops = pll_ops;
if (data->parent_name)
init.parent_names = &data->parent_name;
else
......@@ -360,7 +329,22 @@ static struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
return &pll->hw;
}
static void mtk_clk_unregister_pll(struct clk_hw *hw)
struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
void __iomem *base)
{
struct mtk_clk_pll *pll;
struct clk_hw *hw;
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
return ERR_PTR(-ENOMEM);
hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
return hw;
}
void mtk_clk_unregister_pll(struct clk_hw *hw)
{
struct mtk_clk_pll *pll;
......@@ -423,8 +407,8 @@ int mtk_clk_register_plls(struct device_node *node,
}
EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
static __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
const struct mtk_pll_data *data)
__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
const struct mtk_pll_data *data)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
......
drivers/clk/mediatek/clk-pll.h
View file @ 0e2c9884
......@@ -7,6 +7,7 @@
#ifndef __DRV_CLK_MTK_PLL_H
#define __DRV_CLK_MTK_PLL_H
#include <linux/clk-provider.h>
#include <linux/types.h>
struct clk_ops;
......@@ -20,6 +21,7 @@ struct mtk_pll_div_table {
#define HAVE_RST_BAR BIT(0)
#define PLL_AO BIT(1)
#define POSTDIV_MASK GENMASK(2, 0)
struct mtk_pll_data {
int id;
......@@ -48,10 +50,63 @@ struct mtk_pll_data {
u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
};
/*
* MediaTek PLLs are configured through their pcw value. The pcw value describes
* a divider in the PLL feedback loop which consists of 7 bits for the integer
* part and the remaining bits (if present) for the fractional part. Also they
* have a 3 bit power-of-two post divider.
*/
struct mtk_clk_pll {
struct clk_hw hw;
void __iomem *base_addr;
void __iomem *pd_addr;
void __iomem *pwr_addr;
void __iomem *tuner_addr;
void __iomem *tuner_en_addr;
void __iomem *pcw_addr;
void __iomem *pcw_chg_addr;
void __iomem *en_addr;
const struct mtk_pll_data *data;
};
int mtk_clk_register_plls(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data);
extern const struct clk_ops mtk_pll_ops;
static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
{
return container_of(hw, struct mtk_clk_pll, hw);
}
int mtk_pll_is_prepared(struct clk_hw *hw);
int mtk_pll_prepare(struct clk_hw *hw);
void mtk_pll_unprepare(struct clk_hw *hw);
unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate);
void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
u32 freq, u32 fin);
int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate);
long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate);
struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
const struct mtk_pll_data *data,
void __iomem *base,
const struct clk_ops *pll_ops);
struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
void __iomem *base);
void mtk_clk_unregister_pll(struct clk_hw *hw);
__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
const struct mtk_pll_data *data);
#endif /* __DRV_CLK_MTK_PLL_H */
drivers/clk/mediatek/clk-pllfh.c 0 → 100644
View file @ 0e2c9884
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
*/
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include "clk-mtk.h"
#include "clk-pllfh.h"
#include "clk-fhctl.h"
static DEFINE_SPINLOCK(pllfh_lock);
inline struct mtk_fh *to_mtk_fh(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
return container_of(pll, struct mtk_fh, clk_pll);
}
static int mtk_fhctl_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
struct mtk_fh *fh = to_mtk_fh(hw);
u32 pcw = 0;
u32 postdiv;
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
return fh->ops->hopping(fh, pcw, postdiv);
}
static const struct clk_ops mtk_pllfh_ops = {
.is_prepared = mtk_pll_is_prepared,
.prepare = mtk_pll_prepare,
.unprepare = mtk_pll_unprepare,
.recalc_rate = mtk_pll_recalc_rate,
.round_rate = mtk_pll_round_rate,
.set_rate = mtk_fhctl_set_rate,
};
static struct mtk_pllfh_data *get_pllfh_by_id(struct mtk_pllfh_data *pllfhs,
int num_fhs, int pll_id)
{
int i;
for (i = 0; i < num_fhs; i++)
if (pllfhs[i].data.pll_id == pll_id)
return &pllfhs[i];
return NULL;
}
void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
int num_fhs)
{
void __iomem *base;
struct device_node *node;
u32 num_clocks, pll_id, ssc_rate;
int offset, i;
node = of_find_compatible_node(NULL, NULL, compatible_node);
if (!node) {
pr_err("cannot find \"%s\"\n", compatible_node);
return;
}
base = of_iomap(node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return;
}
num_clocks = of_clk_get_parent_count(node);
if (!num_clocks) {
pr_err("%s(): failed to get clocks property\n", __func__);
return;
}
for (i = 0; i < num_clocks; i++) {
struct mtk_pllfh_data *pllfh;
offset = i * 2;
of_property_read_u32_index(node, "clocks", offset + 1, &pll_id);
of_property_read_u32_index(node,
"mediatek,hopping-ssc-percent",
i, &ssc_rate);
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll_id);
if (!pllfh)
continue;
pllfh->state.fh_enable = 1;
pllfh->state.ssc_rate = ssc_rate;
pllfh->state.base = base;
}
}
static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
{
struct fh_pll_regs *regs = &fh->regs;
const struct fhctl_offset *offset;
void __iomem *base = pllfh_data->state.base;
void __iomem *fhx_base = base + pllfh_data->data.fhx_offset;
offset = fhctl_get_offset_table();
regs->reg_hp_en = base + offset->offset_hp_en;
regs->reg_clk_con = base + offset->offset_clk_con;
regs->reg_rst_con = base + offset->offset_rst_con;
regs->reg_slope0 = base + offset->offset_slope0;
regs->reg_slope1 = base + offset->offset_slope1;
regs->reg_cfg = fhx_base + offset->offset_cfg;
regs->reg_updnlmt = fhx_base + offset->offset_updnlmt;
regs->reg_dds = fhx_base + offset->offset_dds;
regs->reg_dvfs = fhx_base + offset->offset_dvfs;
regs->reg_mon = fhx_base + offset->offset_mon;
fh->pllfh_data = pllfh_data;
fh->lock = &pllfh_lock;
fh->ops = fhctl_get_ops();
}
static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
{
return pllfh && (pllfh->state.fh_enable == 1);
}
static struct clk_hw *
mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
struct mtk_pllfh_data *pllfh_data, void __iomem *base)
{
struct clk_hw *hw;
struct mtk_fh *fh;
fh = kzalloc(sizeof(*fh), GFP_KERNEL);
if (!fh)
return ERR_PTR(-ENOMEM);
pllfh_init(fh, pllfh_data);
hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
&mtk_pllfh_ops);
if (IS_ERR(hw))
kfree(fh);
else
fhctl_hw_init(fh);
return hw;
}
static void mtk_clk_unregister_pllfh(struct clk_hw *hw)
{
struct mtk_fh *fh;
if (!hw)
return;
fh = to_mtk_fh(hw);
clk_hw_unregister(hw);
kfree(fh);
}
int mtk_clk_register_pllfhs(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data)
{
void __iomem *base;
int i;
struct clk_hw *hw;
base = of_iomap(node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return -EINVAL;
}
for (i = 0; i < num_plls; i++) {
const struct mtk_pll_data *pll = &plls[i];
struct mtk_pllfh_data *pllfh;
bool use_fhctl;
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
if (use_fhctl)
hw = mtk_clk_register_pllfh(pll, pllfh, base);
else
hw = mtk_clk_register_pll(pll, base);
if (IS_ERR(hw)) {
pr_err("Failed to register %s clk %s: %ld\n",
use_fhctl ? "fhpll" : "pll", pll->name,
PTR_ERR(hw));
goto err;
}
clk_data->hws[pll->id] = hw;
}
return 0;
err:
while (--i >= 0) {
const struct mtk_pll_data *pll = &plls[i];
struct mtk_pllfh_data *pllfh;
bool use_fhctl;
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
if (use_fhctl)
mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
else
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
}
iounmap(base);
return PTR_ERR(hw);
}
void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data)
{
void __iomem *base = NULL, *fhctl_base = NULL;
int i;
if (!clk_data)
return;
for (i = num_plls; i > 0; i--) {
const struct mtk_pll_data *pll = &plls[i - 1];
struct mtk_pllfh_data *pllfh;
bool use_fhctl;
if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
continue;
pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id);
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
if (use_fhctl) {
fhctl_base = pllfh->state.base;
mtk_clk_unregister_pllfh(clk_data->hws[pll->id]);
} else {
base = mtk_clk_pll_get_base(clk_data->hws[pll->id],
pll);
mtk_clk_unregister_pll(clk_data->hws[pll->id]);
}
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
}
if (fhctl_base)
iounmap(fhctl_base);
iounmap(base);
}
drivers/clk/mediatek/clk-pllfh.h 0 → 100644
View file @ 0e2c9884
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 MediaTek Inc.
* Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
*/
#ifndef __CLK_PLLFH_H
#define __CLK_PLLFH_H
#include "clk-pll.h"
struct fh_pll_state {
void __iomem *base;
u32 fh_enable;
u32 ssc_rate;
};
struct fh_pll_data {
int pll_id;
int fh_id;
u32 fhx_offset;
u32 dds_mask;
u32 slope0_value;
u32 slope1_value;
u32 sfstrx_en;
u32 frddsx_en;
u32 fhctlx_en;
u32 tgl_org;
u32 dvfs_tri;
u32 pcwchg;
u32 dt_val;
u32 df_val;
u32 updnlmt_shft;
u32 msk_frddsx_dys;
u32 msk_frddsx_dts;
};
struct mtk_pllfh_data {
struct fh_pll_state state;
const struct fh_pll_data data;
};
struct fh_pll_regs {
void __iomem *reg_hp_en;
void __iomem *reg_clk_con;
void __iomem *reg_rst_con;
void __iomem *reg_slope0;
void __iomem *reg_slope1;
void __iomem *reg_cfg;
void __iomem *reg_updnlmt;
void __iomem *reg_dds;
void __iomem *reg_dvfs;
void __iomem *reg_mon;
};
struct mtk_fh {
struct mtk_clk_pll clk_pll;
struct fh_pll_regs regs;
struct mtk_pllfh_data *pllfh_data;
const struct fh_operation *ops;
spinlock_t *lock;
};
struct fh_operation {
int (*hopping)(struct mtk_fh *fh, unsigned int new_dds,
unsigned int postdiv);
int (*ssc_enable)(struct mtk_fh *fh, u32 rate);
};
int mtk_clk_register_pllfhs(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_pllfhs,
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_pllfhs(const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data);
void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
int num_pllfhs);
#endif /* __CLK_PLLFH_H */
drivers/clk/microchip/Kconfig
View file @ 0e2c9884
......@@ -5,7 +5,8 @@ config COMMON_CLK_PIC32
config MCHP_CLK_MPFS
bool "Clk driver for PolarFire SoC"
depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST
depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
default SOC_MICROCHIP_POLARFIRE
select AUXILIARY_BUS
help
Supports Clock Configuration for PolarFire SoC
drivers/clk/microchip/clk-mpfs-ccc.c
View file @ 0e2c9884
......@@ -166,6 +166,9 @@ static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_
struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
char *name = devm_kzalloc(dev, 23, GFP_KERNEL);
if (!name)
return -ENOMEM;
snprintf(name, 23, "%s_out%u", parent->name, i);
out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
......@@ -200,6 +203,9 @@ static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clo
struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
char *name = devm_kzalloc(dev, 18, GFP_KERNEL);
if (!name)
return -ENOMEM;
pll_hw->base = data->pll_base[i];
snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);
pll_hw->name = (const char *)name;
......
drivers/clk/qcom/Kconfig
View file @ 0e2c9884
......@@ -401,6 +401,15 @@ config SC_DISPCC_7280
Say Y if you want to support display devices and functionality such as
splash screen.
config SC_DISPCC_8280XP
tristate "SC8280XP Display Clock Controller"
select SC_GCC_8280XP
help
Support for the two display clock controllers on Qualcomm
Technologies, Inc. SC8280XP devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config SC_GCC_7180
tristate "SC7180 Global Clock Controller"
select QCOM_GDSC
......@@ -668,6 +677,15 @@ config SM_DISPCC_6350
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_DISPCC_6375
tristate "SM6375 Display Clock Controller"
depends on SM_GCC_6375
help
Support for the display clock controller on Qualcomm Technologies, Inc
SM6375 devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config SM_DISPCC_8450
tristate "SM8450 Display Clock Controller"
depends on SM_GCC_8450
......@@ -739,6 +757,14 @@ config SM_GCC_8450
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GCC_8550
tristate "SM8550 Global Clock Controller"
select QCOM_GDSC
help
Support for the global clock controller on SM8550 devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config SM_GPUCC_6350
tristate "SM6350 Graphics Clock Controller"
select SM_GCC_6350
......
drivers/clk/qcom/Makefile
View file @ 0e2c9884
......@@ -66,6 +66,7 @@ obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o
obj-$(CONFIG_SC_CAMCC_7280) += camcc-sc7280.o
obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o
obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o
obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o
obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o
obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o
obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o
......@@ -95,6 +96,7 @@ obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
obj-$(CONFIG_SM_DISPCC_6375) += dispcc-sm6375.o
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o
obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o
......@@ -105,6 +107,7 @@ obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o
obj-$(CONFIG_SM_GCC_8550) += gcc-sm8550.o
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
......
drivers/clk/qcom/clk-alpha-pll.c
View file @ 0e2c9884
......@@ -155,6 +155,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
},
[CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATE] = 0x08,
[PLL_OFF_STATUS] = 0x0c,
[PLL_OFF_L_VAL] = 0x10,
[PLL_OFF_ALPHA_VAL] = 0x14,
[PLL_OFF_USER_CTL] = 0x18,
[PLL_OFF_USER_CTL_U] = 0x1c,
[PLL_OFF_CONFIG_CTL] = 0x20,
[PLL_OFF_CONFIG_CTL_U] = 0x24,
[PLL_OFF_CONFIG_CTL_U1] = 0x28,
[PLL_OFF_TEST_CTL] = 0x2c,
[PLL_OFF_TEST_CTL_U] = 0x30,
[PLL_OFF_TEST_CTL_U1] = 0x34,
[PLL_OFF_TEST_CTL_U2] = 0x38,
},
[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATUS] = 0x0c,
......
drivers/clk/qcom/clk-alpha-pll.h
View file @ 0e2c9884
......@@ -18,6 +18,7 @@ enum {
CLK_ALPHA_PLL_TYPE_AGERA,
CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_LUCID_OLE,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
......@@ -38,6 +39,8 @@ enum {
PLL_OFF_TEST_CTL,
PLL_OFF_TEST_CTL_U,
PLL_OFF_TEST_CTL_U1,
PLL_OFF_TEST_CTL_U2,
PLL_OFF_STATE,
PLL_OFF_STATUS,
PLL_OFF_OPMODE,
PLL_OFF_FRAC,
......@@ -160,7 +163,9 @@ extern const struct clk_ops clk_alpha_pll_zonda_ops;
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
......
drivers/clk/qcom/clk-krait.c
View file @ 0e2c9884
......@@ -114,6 +114,8 @@ static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
if (d->lpl)
mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
else
mask <<= d->shift;
spin_lock_irqsave(&krait_clock_reg_lock, flags);
val = krait_get_l2_indirect_reg(d->offset);
......
drivers/clk/qcom/clk-rpm.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/clk-rpmh.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/dispcc-sc8280xp.c 0 → 100644
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/dispcc-sm6350.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/dispcc-sm6375.c 0 → 100644
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/dispcc-sm8250.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gcc-ipq4019.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gcc-ipq806x.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gcc-ipq8074.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gcc-msm8939.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gcc-msm8974.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gcc-sm6125.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gcc-sm8250.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gcc-sm8550.c 0 → 100644
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/gdsc.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/hfpll.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/kpss-xcc.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/krait-cc.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/lpassaudiocc-sc7280.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/lpasscorecc-sc7180.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/mmcc-msm8974.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/reset.c
View file @ 0e2c9884
This diff is collapsed.
drivers/clk/qcom/reset.h
View file @ 0e2c9884
This diff is collapsed.
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h 0 → 100644
View file @ 0e2c9884
This diff is collapsed.
include/dt-bindings/clock/qcom,sm6375-dispcc.h 0 → 100644
View file @ 0e2c9884
This diff is collapsed.
include/dt-bindings/clock/qcom,sm8550-gcc.h 0 → 100644
View file @ 0e2c9884
This diff is collapsed.
include/linux/clk-provider.h
View file @ 0e2c9884
This diff is collapsed.
include/trace/events/clk.h
View file @ 0e2c9884
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7