Commit 0ea001d3 authored by Chris Zhong's avatar Chris Zhong Committed by Heiko Stuebner

ARM: rockchip: disable dapswjdp during suspend

Reset dapswjdp is controlled by JTAG_TRSTN, if the iomux of this pin is
not "jtag_trstn". the AP would think this pin is always high, so it can
not reset before resume. When system resume, but the dapswjdp is not in
a default state, it may Access some illegal address, it cause system
crash during resume.
Let's disable this jtag function by clear the dapdeviceen bit, it
prohibit the dapswjdp to access memory and registers. This bit would
be enable in MASKROM, so we need clear it in suspend everytime.
Signed-off-by: default avatarChris Zhong <zyw@rock-chips.com>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent a0307d18
......@@ -83,6 +83,13 @@ static void rk3288_slp_mode_set(int level)
SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
| SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
/*
* The dapswjdp can not auto reset before resume, that cause it may
* access some illegal address during resume. Let's disable it before
* suspend, and the MASKROM will enable it back.
*/
regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
/* booting address of resuming system is from this register value */
regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
rk3288_bootram_phy);
......
......@@ -55,6 +55,10 @@ static inline void rockchip_suspend_init(void)
#define SGRF_FAST_BOOT_EN BIT(8)
#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
#define RK3288_SGRF_CPU_CON0 (0x40)
#define SGRF_DAPDEVICEEN BIT(0)
#define SGRF_DAPDEVICEEN_WRITE BIT(16)
#define RK3288_CRU_MODE_CON 0x50
#define RK3288_CRU_SEL0_CON 0x60
#define RK3288_CRU_SEL1_CON 0x64
......
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