Commit 0eaa8012 authored by Shirish S's avatar Shirish S Committed by Alex Deucher

amdgpu/gmc_v9: Warn if SDPIF_MMIO_CNTRL_0 is not set

With IOMMU enabled, if SDPIF_MMIO_CNTRL_0 is not set
appropriately the system hangs without any trace
during S3.

To ease debug and to ensure that the failure, if any,
was caused by a race conditions that disabled write access to
SDPIF_MMIO_CNTRL_0 register, warn the user about it.
Signed-off-by: default avatarShirish S <shirish.s@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 92e00593
...@@ -1545,8 +1545,11 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -1545,8 +1545,11 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
*/ */
void gmc_v9_0_restore_registers(struct amdgpu_device *adev) void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
{ {
if (adev->asic_type == CHIP_RAVEN) if (adev->asic_type == CHIP_RAVEN) {
WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
WARN_ON(adev->gmc.sdpif_register !=
RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
}
} }
/** /**
......
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