Commit 0f66f96d authored by Linus Torvalds's avatar Linus Torvalds

Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm: (37 commits)
  ARM: 5673/1: U300 fix initsection compile warning
  ARM: Fix broken highmem support
  mx31moboard: invert sdhc ro signal sense
  ARM: S3C24XX: Fix clkout mpx error
  ARM: S3C64XX: serial: Fix a typo in Kconfig
  IXP4xx: Fix IO_SPACE_LIMIT for 2.6.31-rc core PCI changes
  OMAP3: RX51: Updated rx51_defconfig
  OMAP2/3: mmc-twl4030: Free up MMC regulators while cleaning up
  OMAP3: RX51: Define TWL4030 USB transceiver in board file
  OMAP3: Overo: Fix smsc911x platform device resource value
  OMAP3: Fix omap3 sram virtual addres overlap vmalloc space after increasing vmalloc size
  OMAP2/3: DMA errata correction
  OMAP: Fix testing of cpu defines for mach-omap1
  OMAP3: Overo: add missing pen-down GPIO definition
  OMAP: GPIO: clear/restore level/edge detect settings on mask/unmask
  OMAP3: PM: Fix wrong sequence in suspend.
  OMAP: PM: CPUfreq: obey min/max settings of policy
  OMAP2/3/4: UART: allow in-order port traversal
  OMAP2/3/4: UART: Allow per-UART disabling wakeup for serial ports
  OMAP3: Fixed crash bug with serial + suspend
  ...
parents 894ef820 a2bb9f4d
...@@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y ...@@ -282,7 +282,7 @@ CONFIG_ALIGNMENT_TRAP=y
# #
CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0" CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs rootflags=bulk_read,no_chk_data_crc rw console=ttyMTD,log console=tty0 console=ttyS2,115200n8"
# CONFIG_XIP_KERNEL is not set # CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set # CONFIG_KEXEC is not set
...@@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y ...@@ -1354,7 +1354,7 @@ CONFIG_USB_OTG_UTILS=y
# CONFIG_USB_GPIO_VBUS is not set # CONFIG_USB_GPIO_VBUS is not set
# CONFIG_ISP1301_OMAP is not set # CONFIG_ISP1301_OMAP is not set
CONFIG_TWL4030_USB=y CONFIG_TWL4030_USB=y
CONFIG_MMC=m CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set # CONFIG_MMC_DEBUG is not set
# CONFIG_MMC_UNSAFE_RESUME is not set # CONFIG_MMC_UNSAFE_RESUME is not set
...@@ -1449,7 +1449,8 @@ CONFIG_RTC_DRV_TWL4030=m ...@@ -1449,7 +1449,8 @@ CONFIG_RTC_DRV_TWL4030=m
# on-CPU RTC drivers # on-CPU RTC drivers
# #
# CONFIG_DMADEVICES is not set # CONFIG_DMADEVICES is not set
# CONFIG_REGULATOR is not set CONFIG_REGULATOR=y
CONFIG_REGULATOR_TWL4030=y
# CONFIG_UIO is not set # CONFIG_UIO is not set
# CONFIG_STAGING is not set # CONFIG_STAGING is not set
......
...@@ -201,7 +201,8 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn } ...@@ -201,7 +201,8 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
struct membank { struct membank {
unsigned long start; unsigned long start;
unsigned long size; unsigned long size;
int node; unsigned short node;
unsigned short highmem;
}; };
struct meminfo { struct meminfo {
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#include <mach/hardware.h> #include <mach/hardware.h>
#define IO_SPACE_LIMIT 0xffff0000 #define IO_SPACE_LIMIT 0x0000ffff
extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
......
...@@ -63,7 +63,7 @@ static struct imxuart_platform_data uart_pdata = { ...@@ -63,7 +63,7 @@ static struct imxuart_platform_data uart_pdata = {
static int devboard_sdhc2_get_ro(struct device *dev) static int devboard_sdhc2_get_ro(struct device *dev)
{ {
return gpio_get_value(SDHC2_WP); return !gpio_get_value(SDHC2_WP);
} }
static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq, static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
......
...@@ -67,7 +67,7 @@ static unsigned int marxbot_pins[] = { ...@@ -67,7 +67,7 @@ static unsigned int marxbot_pins[] = {
static int marxbot_sdhc2_get_ro(struct device *dev) static int marxbot_sdhc2_get_ro(struct device *dev)
{ {
return gpio_get_value(SDHC2_WP); return !gpio_get_value(SDHC2_WP);
} }
static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq, static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
......
...@@ -94,7 +94,7 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = { ...@@ -94,7 +94,7 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
static int moboard_sdhc1_get_ro(struct device *dev) static int moboard_sdhc1_get_ro(struct device *dev)
{ {
return gpio_get_value(SDHC1_WP); return !gpio_get_value(SDHC1_WP);
} }
static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq, static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
......
...@@ -24,15 +24,6 @@ ...@@ -24,15 +24,6 @@
#include "devices.h" #include "devices.h"
static unsigned int pcm037_eet_pins[] = { static unsigned int pcm037_eet_pins[] = {
/* SPI #1 */
MX31_PIN_CSPI1_MISO__MISO,
MX31_PIN_CSPI1_MOSI__MOSI,
MX31_PIN_CSPI1_SCLK__SCLK,
MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
MX31_PIN_CSPI1_SS0__SS0,
MX31_PIN_CSPI1_SS1__SS1,
MX31_PIN_CSPI1_SS2__SS2,
/* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */ /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO), IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
/* GPIO keys */ /* GPIO keys */
......
...@@ -141,7 +141,7 @@ static inline void board_smc91x_init(void) ...@@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
static void __init omap_2430sdp_init_irq(void) static void __init omap_2430sdp_init_irq(void)
{ {
omap2_init_common_hw(NULL); omap2_init_common_hw(NULL, NULL);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
} }
......
...@@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = { ...@@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = {
static void __init omap_3430sdp_init_irq(void) static void __init omap_3430sdp_init_irq(void)
{ {
omap2_init_common_hw(hyb18m512160af6_sdrc_params); omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
} }
......
...@@ -59,7 +59,7 @@ static void __init gic_init_irq(void) ...@@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
static void __init omap_4430sdp_init_irq(void) static void __init omap_4430sdp_init_irq(void)
{ {
omap2_init_common_hw(NULL); omap2_init_common_hw(NULL, NULL);
#ifdef CONFIG_OMAP_32K_TIMER #ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(1); omap2_gp_clockevent_set_gptimer(1);
#endif #endif
......
...@@ -250,7 +250,7 @@ static inline void __init apollon_init_smc91x(void) ...@@ -250,7 +250,7 @@ static inline void __init apollon_init_smc91x(void)
static void __init omap_apollon_init_irq(void) static void __init omap_apollon_init_irq(void)
{ {
omap2_init_common_hw(NULL); omap2_init_common_hw(NULL, NULL);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
apollon_init_smc91x(); apollon_init_smc91x();
......
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
static void __init omap_generic_init_irq(void) static void __init omap_generic_init_irq(void)
{ {
omap2_init_common_hw(NULL); omap2_init_common_hw(NULL, NULL);
omap_init_irq(); omap_init_irq();
} }
......
...@@ -270,7 +270,7 @@ static void __init h4_init_flash(void) ...@@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
static void __init omap_h4_init_irq(void) static void __init omap_h4_init_irq(void)
{ {
omap2_init_common_hw(NULL); omap2_init_common_hw(NULL, NULL);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
h4_init_flash(); h4_init_flash();
......
...@@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void) ...@@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
static void __init omap_ldp_init_irq(void) static void __init omap_ldp_init_irq(void)
{ {
omap2_init_common_hw(NULL); omap2_init_common_hw(NULL, NULL);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
ldp_init_smsc911x(); ldp_init_smsc911x();
......
...@@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void) ...@@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void)
static void __init omap3_beagle_init_irq(void) static void __init omap3_beagle_init_irq(void)
{ {
omap2_init_common_hw(mt46h32m32lf6_sdrc_params); omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq(); omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER #ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12); omap2_gp_clockevent_set_gptimer(12);
...@@ -408,6 +409,10 @@ static void __init omap3_beagle_init(void) ...@@ -408,6 +409,10 @@ static void __init omap3_beagle_init(void)
usb_musb_init(); usb_musb_init();
omap3beagle_flash_init(); omap3beagle_flash_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
} }
static void __init omap3_beagle_map_io(void) static void __init omap3_beagle_map_io(void)
......
...@@ -280,7 +280,7 @@ struct spi_board_info omap3evm_spi_board_info[] = { ...@@ -280,7 +280,7 @@ struct spi_board_info omap3evm_spi_board_info[] = {
static void __init omap3_evm_init_irq(void) static void __init omap3_evm_init_irq(void)
{ {
omap2_init_common_hw(mt46h32m32lf6_sdrc_params); omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
omap3evm_init_smc911x(); omap3evm_init_smc911x();
......
...@@ -40,6 +40,7 @@ ...@@ -40,6 +40,7 @@
#include <mach/mcspi.h> #include <mach/mcspi.h>
#include <mach/usb.h> #include <mach/usb.h>
#include <mach/keypad.h> #include <mach/keypad.h>
#include <mach/mux.h>
#include "sdram-micron-mt46h32m32lf-6.h" #include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h" #include "mmc-twl4030.h"
...@@ -310,7 +311,8 @@ static int __init omap3pandora_i2c_init(void) ...@@ -310,7 +311,8 @@ static int __init omap3pandora_i2c_init(void)
static void __init omap3pandora_init_irq(void) static void __init omap3pandora_init_irq(void)
{ {
omap2_init_common_hw(mt46h32m32lf6_sdrc_params); omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
} }
...@@ -397,6 +399,10 @@ static void __init omap3pandora_init(void) ...@@ -397,6 +399,10 @@ static void __init omap3pandora_init(void)
omap3pandora_ads7846_init(); omap3pandora_ads7846_init();
pandora_keys_gpio_init(); pandora_keys_gpio_init();
usb_musb_init(); usb_musb_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
} }
static void __init omap3pandora_map_io(void) static void __init omap3pandora_map_io(void)
......
...@@ -44,6 +44,7 @@ ...@@ -44,6 +44,7 @@
#include <mach/gpmc.h> #include <mach/gpmc.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/nand.h> #include <mach/nand.h>
#include <mach/mux.h>
#include <mach/usb.h> #include <mach/usb.h>
#include "sdram-micron-mt46h32m32lf-6.h" #include "sdram-micron-mt46h32m32lf-6.h"
...@@ -51,6 +52,7 @@ ...@@ -51,6 +52,7 @@
#define OVERO_GPIO_BT_XGATE 15 #define OVERO_GPIO_BT_XGATE 15
#define OVERO_GPIO_W2W_NRESET 16 #define OVERO_GPIO_W2W_NRESET 16
#define OVERO_GPIO_PENDOWN 114
#define OVERO_GPIO_BT_NRESET 164 #define OVERO_GPIO_BT_NRESET 164
#define OVERO_GPIO_USBH_CPEN 168 #define OVERO_GPIO_USBH_CPEN 168
#define OVERO_GPIO_USBH_NRESET 183 #define OVERO_GPIO_USBH_NRESET 183
...@@ -146,7 +148,7 @@ static struct platform_device overo_smsc911x_device = { ...@@ -146,7 +148,7 @@ static struct platform_device overo_smsc911x_device = {
.name = "smsc911x", .name = "smsc911x",
.id = -1, .id = -1,
.num_resources = ARRAY_SIZE(overo_smsc911x_resources), .num_resources = ARRAY_SIZE(overo_smsc911x_resources),
.resource = &overo_smsc911x_resources, .resource = overo_smsc911x_resources,
.dev = { .dev = {
.platform_data = &overo_smsc911x_config, .platform_data = &overo_smsc911x_config,
}, },
...@@ -360,7 +362,8 @@ static int __init overo_i2c_init(void) ...@@ -360,7 +362,8 @@ static int __init overo_i2c_init(void)
static void __init overo_init_irq(void) static void __init overo_init_irq(void)
{ {
omap2_init_common_hw(mt46h32m32lf6_sdrc_params); omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
} }
...@@ -395,6 +398,10 @@ static void __init overo_init(void) ...@@ -395,6 +398,10 @@ static void __init overo_init(void)
overo_ads7846_init(); overo_ads7846_init();
overo_init_smsc911x(); overo_init_smsc911x();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
if ((gpio_request(OVERO_GPIO_W2W_NRESET, if ((gpio_request(OVERO_GPIO_W2W_NRESET,
"OVERO_GPIO_W2W_NRESET") == 0) && "OVERO_GPIO_W2W_NRESET") == 0) &&
(gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) { (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
......
...@@ -278,6 +278,10 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = { ...@@ -278,6 +278,10 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
.setup = rx51_twlgpio_setup, .setup = rx51_twlgpio_setup,
}; };
static struct twl4030_usb_data rx51_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_platform_data rx51_twldata = { static struct twl4030_platform_data rx51_twldata = {
.irq_base = TWL4030_IRQ_BASE, .irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END, .irq_end = TWL4030_IRQ_END,
...@@ -286,6 +290,7 @@ static struct twl4030_platform_data rx51_twldata = { ...@@ -286,6 +290,7 @@ static struct twl4030_platform_data rx51_twldata = {
.gpio = &rx51_gpio_data, .gpio = &rx51_gpio_data,
.keypad = &rx51_kp_data, .keypad = &rx51_kp_data,
.madc = &rx51_madc_data, .madc = &rx51_madc_data,
.usb = &rx51_usb_data,
.vaux1 = &rx51_vaux1, .vaux1 = &rx51_vaux1,
.vaux2 = &rx51_vaux2, .vaux2 = &rx51_vaux2,
......
...@@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = { ...@@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = {
static void __init rx51_init_irq(void) static void __init rx51_init_irq(void)
{ {
omap2_init_common_hw(NULL); omap2_init_common_hw(NULL, NULL);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
} }
...@@ -75,6 +75,10 @@ static void __init rx51_init(void) ...@@ -75,6 +75,10 @@ static void __init rx51_init(void)
omap_serial_init(); omap_serial_init();
usb_musb_init(); usb_musb_init();
rx51_peripherals_init(); rx51_peripherals_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
} }
static void __init rx51_map_io(void) static void __init rx51_map_io(void)
......
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
static void __init omap_zoom2_init_irq(void) static void __init omap_zoom2_init_irq(void)
{ {
omap2_init_common_hw(NULL); omap2_init_common_hw(NULL, NULL);
omap_init_irq(); omap_init_irq();
omap_gpio_init(); omap_gpio_init();
} }
......
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/clockdomain.h> #include <mach/clockdomain.h>
#include <mach/cpu.h> #include <mach/cpu.h>
#include <mach/prcm.h>
#include <asm/div64.h> #include <asm/div64.h>
#include <mach/sdrc.h> #include <mach/sdrc.h>
...@@ -38,8 +39,6 @@ ...@@ -38,8 +39,6 @@
#include "cm-regbits-24xx.h" #include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h" #include "cm-regbits-34xx.h"
#define MAX_CLOCK_ENABLE_WAIT 100000
/* DPLL rate rounding: minimum DPLL multiplier, divider values */ /* DPLL rate rounding: minimum DPLL multiplier, divider values */
#define DPLL_MIN_MULTIPLIER 1 #define DPLL_MIN_MULTIPLIER 1
#define DPLL_MIN_DIVIDER 1 #define DPLL_MIN_DIVIDER 1
...@@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk) ...@@ -274,83 +273,97 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
} }
/** /**
* omap2_wait_clock_ready - wait for clock to enable * omap2_clk_dflt_find_companion - find companion clock to @clk
* @reg: physical address of clock IDLEST register * @clk: struct clk * to find the companion clock of
* @mask: value to mask against to determine if the clock is active * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
* @name: name of the clock (for printk) * @other_bit: u8 ** to return the companion clock bit shift in
*
* Note: We don't need special code here for INVERT_ENABLE for the
* time being since INVERT_ENABLE only applies to clocks enabled by
* CM_CLKEN_PLL
* *
* Returns 1 if the clock enabled in time, or 0 if it failed to enable * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
* in roughly MAX_CLOCK_ENABLE_WAIT microseconds. * just a matter of XORing the bits.
*
* Some clocks don't have companion clocks. For example, modules with
* only an interface clock (such as MAILBOXES) don't have a companion
* clock. Right now, this code relies on the hardware exporting a bit
* in the correct companion register that indicates that the
* nonexistent 'companion clock' is active. Future patches will
* associate this type of code with per-module data structures to
* avoid this issue, and remove the casts. No return value.
*/ */
int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
u8 *other_bit)
{ {
int i = 0; u32 r;
int ena = 0;
/* /*
* 24xx uses 0 to indicate not ready, and 1 to indicate ready. * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
* 34xx reverses this, just to keep us on our toes * it's just a matter of XORing the bits.
*/ */
if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
ena = mask;
else if (cpu_mask & RATE_IN_343X)
ena = 0;
/* Wait for lock */
while (((__raw_readl(reg) & mask) != ena) &&
(i++ < MAX_CLOCK_ENABLE_WAIT)) {
udelay(1);
}
if (i <= MAX_CLOCK_ENABLE_WAIT)
pr_debug("Clock %s stable after %d loops\n", name, i);
else
printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
name, MAX_CLOCK_ENABLE_WAIT);
return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
};
*other_reg = (__force void __iomem *)r;
*other_bit = clk->enable_bit;
}
/* /**
* Note: We don't need special code here for INVERT_ENABLE * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
* for the time being since INVERT_ENABLE only applies to clocks enabled by * @clk: struct clk * to find IDLEST info for
* CM_CLKEN_PLL * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
* @idlest_bit: u8 ** to return the CM_IDLEST bit shift in
*
* Return the CM_IDLEST register address and bit shift corresponding
* to the module that "owns" this clock. This default code assumes
* that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
* the IDLEST register address ID corresponds to the CM_*CLKEN
* register address ID (e.g., that CM_FCLKEN2 corresponds to
* CM_IDLEST2). This is not true for all modules. No return value.
*/ */
static void omap2_clk_wait_ready(struct clk *clk) void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
u8 *idlest_bit)
{ {
void __iomem *reg, *other_reg, *st_reg; u32 r;
u32 bit;
/* r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
* REVISIT: This code is pretty ugly. It would be nice to generalize *idlest_reg = (__force void __iomem *)r;
* it and pull it into struct clk itself somehow. *idlest_bit = clk->enable_bit;
*/ }
reg = clk->enable_reg;
/* /**
* Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes * omap2_module_wait_ready - wait for an OMAP module to leave IDLE
* it's just a matter of XORing the bits. * @clk: struct clk * belonging to the module
*/ *
other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); * If the necessary clocks for the OMAP hardware IP block that
* corresponds to clock @clk are enabled, then wait for the module to
* indicate readiness (i.e., to leave IDLE). This code does not
* belong in the clock code and will be moved in the medium term to
* module-dependent code. No return value.
*/
static void omap2_module_wait_ready(struct clk *clk)
{
void __iomem *companion_reg, *idlest_reg;
u8 other_bit, idlest_bit;
/* Not all modules have multiple clocks that their IDLEST depends on */
if (clk->ops->find_companion) {
clk->ops->find_companion(clk, &companion_reg, &other_bit);
if (!(__raw_readl(companion_reg) & (1 << other_bit)))
return;
}
/* Check if both functional and interface clocks clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit);
* are running. */
bit = 1 << clk->enable_bit;
if (!(__raw_readl(other_reg) & bit))
return;
st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
omap2_wait_clock_ready(st_reg, bit, clk->name); omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name);
} }
static int omap2_dflt_clk_enable(struct clk *clk) int omap2_dflt_clk_enable(struct clk *clk)
{ {
u32 v; u32 v;
if (unlikely(clk->enable_reg == NULL)) { if (unlikely(clk->enable_reg == NULL)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n", pr_err("clock.c: Enable for %s without enable code\n",
clk->name); clk->name);
return 0; /* REVISIT: -EINVAL */ return 0; /* REVISIT: -EINVAL */
} }
...@@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk) ...@@ -363,26 +376,13 @@ static int omap2_dflt_clk_enable(struct clk *clk)
__raw_writel(v, clk->enable_reg); __raw_writel(v, clk->enable_reg);
v = __raw_readl(clk->enable_reg); /* OCP barrier */ v = __raw_readl(clk->enable_reg); /* OCP barrier */
return 0; if (clk->ops->find_idlest)
} omap2_module_wait_ready(clk);
static int omap2_dflt_clk_enable_wait(struct clk *clk) return 0;
{
int ret;
if (!clk->enable_reg) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
return 0; /* REVISIT: -EINVAL */
}
ret = omap2_dflt_clk_enable(clk);
if (ret == 0)
omap2_clk_wait_ready(clk);
return ret;
} }
static void omap2_dflt_clk_disable(struct clk *clk) void omap2_dflt_clk_disable(struct clk *clk)
{ {
u32 v; u32 v;
...@@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk) ...@@ -406,8 +406,10 @@ static void omap2_dflt_clk_disable(struct clk *clk)
} }
const struct clkops clkops_omap2_dflt_wait = { const struct clkops clkops_omap2_dflt_wait = {
.enable = omap2_dflt_clk_enable_wait, .enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable, .disable = omap2_dflt_clk_disable,
.find_companion = omap2_clk_dflt_find_companion,
.find_idlest = omap2_clk_dflt_find_idlest,
}; };
const struct clkops clkops_omap2_dflt = { const struct clkops clkops_omap2_dflt = {
......
...@@ -65,6 +65,12 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); ...@@ -65,6 +65,12 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
u32 omap2_get_dpll_rate(struct clk *clk); u32 omap2_get_dpll_rate(struct clk *clk);
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
void omap2_clk_prepare_for_reboot(void); void omap2_clk_prepare_for_reboot(void);
int omap2_dflt_clk_enable(struct clk *clk);
void omap2_dflt_clk_disable(struct clk *clk);
void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
u8 *other_bit);
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
u8 *idlest_bit);
extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_omap2_dflt; extern const struct clkops clkops_omap2_dflt;
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include <mach/clock.h> #include <mach/clock.h>
#include <mach/sram.h> #include <mach/sram.h>
#include <mach/prcm.h>
#include <asm/div64.h> #include <asm/div64.h>
#include <asm/clkdev.h> #include <asm/clkdev.h>
...@@ -43,6 +44,18 @@ ...@@ -43,6 +44,18 @@
static const struct clkops clkops_oscck; static const struct clkops clkops_oscck;
static const struct clkops clkops_fixed; static const struct clkops clkops_fixed;
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
/* 2430 I2CHS has non-standard IDLEST register */
static const struct clkops clkops_omap2430_i2chs_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap2430_clk_i2chs_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
#include "clock24xx.h" #include "clock24xx.h"
struct omap_clk { struct omap_clk {
...@@ -239,6 +252,26 @@ static void __iomem *prcm_clksrc_ctrl; ...@@ -239,6 +252,26 @@ static void __iomem *prcm_clksrc_ctrl;
* Omap24xx specific clock functions * Omap24xx specific clock functions
*-------------------------------------------------------------------------*/ *-------------------------------------------------------------------------*/
/**
* omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
*
* OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the
* CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function
* passes back the correct CM_IDLEST register address for I2CHS
* modules. No return value.
*/
static void omap2430_clk_i2chs_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit)
{
*idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST);
*idlest_bit = clk->enable_bit;
}
/** /**
* omap2xxx_clk_get_core_rate - return the CORE_CLK rate * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
* @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck")
...@@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk) ...@@ -325,8 +358,8 @@ static int omap2_clk_fixed_enable(struct clk *clk)
else if (clk == &apll54_ck) else if (clk == &apll54_ck)
cval = OMAP24XX_ST_54M_APLL; cval = OMAP24XX_ST_54M_APLL;
omap2_wait_clock_ready(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval,
clk->name); clk->name);
/* /*
* REVISIT: Should we return an error code if omap2_wait_clock_ready() * REVISIT: Should we return an error code if omap2_wait_clock_ready()
......
...@@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = { ...@@ -2337,7 +2337,7 @@ static struct clk i2c2_fck = {
static struct clk i2chs2_fck = { static struct clk i2chs2_fck = {
.name = "i2c_fck", .name = "i2c_fck",
.ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2430_i2chs_wait,
.id = 2, .id = 2,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm", .clkdm_name = "core_l4_clkdm",
...@@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = { ...@@ -2370,7 +2370,7 @@ static struct clk i2c1_fck = {
static struct clk i2chs1_fck = { static struct clk i2chs1_fck = {
.name = "i2c_fck", .name = "i2c_fck",
.ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2430_i2chs_wait,
.id = 1, .id = 1,
.parent = &func_96m_ck, .parent = &func_96m_ck,
.clkdm_name = "core_l4_clkdm", .clkdm_name = "core_l4_clkdm",
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
* OMAP3-specific clock framework functions * OMAP3-specific clock framework functions
* *
* Copyright (C) 2007-2008 Texas Instruments, Inc. * Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation * Copyright (C) 2007-2009 Nokia Corporation
* *
* Written by Paul Walmsley * Written by Paul Walmsley
* Testing and integration fixes by Jouni Högander * Testing and integration fixes by Jouni Högander
...@@ -41,6 +41,37 @@ ...@@ -41,6 +41,37 @@
static const struct clkops clkops_noncore_dpll_ops; static const struct clkops clkops_noncore_dpll_ops;
static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit);
static const struct clkops clkops_omap3430es2_ssi_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_ssi_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
.enable = omap2_dflt_clk_enable,
.disable = omap2_dflt_clk_disable,
.find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
.find_companion = omap2_clk_dflt_find_companion,
};
#include "clock34xx.h" #include "clock34xx.h"
struct omap_clk { struct omap_clk {
...@@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = { ...@@ -157,10 +188,13 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X), CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
...@@ -193,18 +227,21 @@ static struct omap_clk omap34xx_clks[] = { ...@@ -193,18 +227,21 @@ static struct omap_clk omap34xx_clks[] = {
CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
CLK(NULL, "ssi_ick", &ssi_ick, CK_343X), CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
CLK("omap_rng", "ick", &rng_ick, CK_343X), CLK("omap_rng", "ick", &rng_ick, CK_343X),
CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
CLK(NULL, "des1_ick", &des1_ick, CK_343X), CLK(NULL, "des1_ick", &des1_ick, CK_343X),
CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X), CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X), CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X), CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X), CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
CLK("omapfb", "ick", &dss_ick, CK_343X), CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
CLK(NULL, "cam_ick", &cam_ick, CK_343X), CLK(NULL, "cam_ick", &cam_ick, CK_343X),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
...@@ -300,6 +337,73 @@ static struct omap_clk omap34xx_clks[] = { ...@@ -300,6 +337,73 @@ static struct omap_clk omap34xx_clks[] = {
*/ */
#define SDRC_MPURATE_LOOPS 96 #define SDRC_MPURATE_LOOPS 96
/**
* omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
*
* The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
* from the CM_{I,F}CLKEN bit. Pass back the correct info via
* @idlest_reg and @idlest_bit. No return value.
*/
static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
*idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
}
/**
* omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
*
* Some OMAP modules on OMAP3 ES2+ chips have both initiator and
* target IDLEST bits. For our purposes, we are concerned with the
* target IDLEST bits, which exist at a different bit position than
* the *CLKEN bit position for these modules (DSS and USBHOST) (The
* default find_idlest code assumes that they are at the same
* position.) No return value.
*/
static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
/* USBHOST_IDLE has same shift */
*idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
}
/**
* omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
* @clk: struct clk * being enabled
* @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
* @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
*
* The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
* shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
* @idlest_reg and @idlest_bit. No return value.
*/
static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
void __iomem **idlest_reg,
u8 *idlest_bit)
{
u32 r;
r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
*idlest_reg = (__force void __iomem *)r;
*idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
}
/** /**
* omap3_dpll_recalc - recalculate DPLL rate * omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk * @clk: DPLL struct clk
...@@ -725,7 +829,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -725,7 +829,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
u32 unlock_dll = 0; u32 unlock_dll = 0;
u32 c; u32 c;
unsigned long validrate, sdrcrate, mpurate; unsigned long validrate, sdrcrate, mpurate;
struct omap_sdrc_params *sp; struct omap_sdrc_params *sdrc_cs0;
struct omap_sdrc_params *sdrc_cs1;
int ret;
if (!clk || !rate) if (!clk || !rate)
return -EINVAL; return -EINVAL;
...@@ -743,8 +849,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -743,8 +849,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
else else
sdrcrate >>= ((clk->rate / rate) >> 1); sdrcrate >>= ((clk->rate / rate) >> 1);
sp = omap2_sdrc_get_params(sdrcrate); ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
if (!sp) if (ret)
return -EINVAL; return -EINVAL;
if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) { if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
...@@ -765,12 +871,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) ...@@ -765,12 +871,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate); validrate);
pr_debug("clock: SDRC timing params used: %08x %08x %08x\n", pr_debug("clock: SDRC CS0 timing params used:"
sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
sp->actim_ctrlb, new_div, unlock_dll, c, if (sdrc_cs1)
sp->mr, rate > clk->rate); pr_debug("clock: SDRC CS1 timing params used: "
" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
if (sdrc_cs1)
omap3_configure_core_dpll(
new_div, unlock_dll, c, rate > clk->rate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
else
omap3_configure_core_dpll(
new_div, unlock_dll, c, rate > clk->rate,
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
0, 0, 0, 0);
return 0; return 0;
} }
......
...@@ -1568,7 +1568,7 @@ static const struct clksel ssi_ssr_clksel[] = { ...@@ -1568,7 +1568,7 @@ static const struct clksel ssi_ssr_clksel[] = {
{ .parent = NULL } { .parent = NULL }
}; };
static struct clk ssi_ssr_fck = { static struct clk ssi_ssr_fck_3430es1 = {
.name = "ssi_ssr_fck", .name = "ssi_ssr_fck",
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.init = &omap2_init_clksel_parent, .init = &omap2_init_clksel_parent,
...@@ -1581,10 +1581,31 @@ static struct clk ssi_ssr_fck = { ...@@ -1581,10 +1581,31 @@ static struct clk ssi_ssr_fck = {
.recalc = &omap2_clksel_recalc, .recalc = &omap2_clksel_recalc,
}; };
static struct clk ssi_sst_fck = { static struct clk ssi_ssr_fck_3430es2 = {
.name = "ssi_ssr_fck",
.ops = &clkops_omap3430es2_ssi_wait,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
.clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
.clksel = ssi_ssr_clksel,
.clkdm_name = "core_l4_clkdm",
.recalc = &omap2_clksel_recalc,
};
static struct clk ssi_sst_fck_3430es1 = {
.name = "ssi_sst_fck", .name = "ssi_sst_fck",
.ops = &clkops_null, .ops = &clkops_null,
.parent = &ssi_ssr_fck, .parent = &ssi_ssr_fck_3430es1,
.fixed_div = 2,
.recalc = &omap2_fixed_divisor_recalc,
};
static struct clk ssi_sst_fck_3430es2 = {
.name = "ssi_sst_fck",
.ops = &clkops_null,
.parent = &ssi_ssr_fck_3430es2,
.fixed_div = 2, .fixed_div = 2,
.recalc = &omap2_fixed_divisor_recalc, .recalc = &omap2_fixed_divisor_recalc,
}; };
...@@ -1606,9 +1627,19 @@ static struct clk core_l3_ick = { ...@@ -1606,9 +1627,19 @@ static struct clk core_l3_ick = {
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk hsotgusb_ick = { static struct clk hsotgusb_ick_3430es1 = {
.name = "hsotgusb_ick", .name = "hsotgusb_ick",
.ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt,
.parent = &core_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.clkdm_name = "core_l3_clkdm",
.recalc = &followparent_recalc,
};
static struct clk hsotgusb_ick_3430es2 = {
.name = "hsotgusb_ick",
.ops = &clkops_omap3430es2_hsotgusb_wait,
.parent = &core_l3_ick, .parent = &core_l3_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
...@@ -1947,7 +1978,7 @@ static struct clk ssi_l4_ick = { ...@@ -1947,7 +1978,7 @@ static struct clk ssi_l4_ick = {
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk ssi_ick = { static struct clk ssi_ick_3430es1 = {
.name = "ssi_ick", .name = "ssi_ick",
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.parent = &ssi_l4_ick, .parent = &ssi_l4_ick,
...@@ -1957,6 +1988,16 @@ static struct clk ssi_ick = { ...@@ -1957,6 +1988,16 @@ static struct clk ssi_ick = {
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk ssi_ick_3430es2 = {
.name = "ssi_ick",
.ops = &clkops_omap3430es2_ssi_wait,
.parent = &ssi_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
.enable_bit = OMAP3430_EN_SSI_SHIFT,
.clkdm_name = "core_l4_clkdm",
.recalc = &followparent_recalc,
};
/* REVISIT: Technically the TRM claims that this is CORE_CLK based, /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
* but l4_ick makes more sense to me */ * but l4_ick makes more sense to me */
...@@ -2024,7 +2065,7 @@ static struct clk des1_ick = { ...@@ -2024,7 +2065,7 @@ static struct clk des1_ick = {
}; };
/* DSS */ /* DSS */
static struct clk dss1_alwon_fck = { static struct clk dss1_alwon_fck_3430es1 = {
.name = "dss1_alwon_fck", .name = "dss1_alwon_fck",
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
.parent = &dpll4_m4x2_ck, .parent = &dpll4_m4x2_ck,
...@@ -2034,6 +2075,16 @@ static struct clk dss1_alwon_fck = { ...@@ -2034,6 +2075,16 @@ static struct clk dss1_alwon_fck = {
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk dss1_alwon_fck_3430es2 = {
.name = "dss1_alwon_fck",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &dpll4_m4x2_ck,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_EN_DSS1_SHIFT,
.clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
static struct clk dss_tv_fck = { static struct clk dss_tv_fck = {
.name = "dss_tv_fck", .name = "dss_tv_fck",
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
...@@ -2067,7 +2118,7 @@ static struct clk dss2_alwon_fck = { ...@@ -2067,7 +2118,7 @@ static struct clk dss2_alwon_fck = {
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk dss_ick = { static struct clk dss_ick_3430es1 = {
/* Handles both L3 and L4 clocks */ /* Handles both L3 and L4 clocks */
.name = "dss_ick", .name = "dss_ick",
.ops = &clkops_omap2_dflt, .ops = &clkops_omap2_dflt,
...@@ -2079,6 +2130,18 @@ static struct clk dss_ick = { ...@@ -2079,6 +2130,18 @@ static struct clk dss_ick = {
.recalc = &followparent_recalc, .recalc = &followparent_recalc,
}; };
static struct clk dss_ick_3430es2 = {
/* Handles both L3 and L4 clocks */
.name = "dss_ick",
.ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &l4_ick,
.init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
.enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
.clkdm_name = "dss_clkdm",
.recalc = &followparent_recalc,
};
/* CAM */ /* CAM */
static struct clk cam_mclk = { static struct clk cam_mclk = {
...@@ -2118,7 +2181,7 @@ static struct clk csi2_96m_fck = { ...@@ -2118,7 +2181,7 @@ static struct clk csi2_96m_fck = {
static struct clk usbhost_120m_fck = { static struct clk usbhost_120m_fck = {
.name = "usbhost_120m_fck", .name = "usbhost_120m_fck",
.ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap2_dflt,
.parent = &dpll5_m2_ck, .parent = &dpll5_m2_ck,
.init = &omap2_init_clk_clkdm, .init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
...@@ -2129,7 +2192,7 @@ static struct clk usbhost_120m_fck = { ...@@ -2129,7 +2192,7 @@ static struct clk usbhost_120m_fck = {
static struct clk usbhost_48m_fck = { static struct clk usbhost_48m_fck = {
.name = "usbhost_48m_fck", .name = "usbhost_48m_fck",
.ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &omap_48m_fck, .parent = &omap_48m_fck,
.init = &omap2_init_clk_clkdm, .init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
...@@ -2141,7 +2204,7 @@ static struct clk usbhost_48m_fck = { ...@@ -2141,7 +2204,7 @@ static struct clk usbhost_48m_fck = {
static struct clk usbhost_ick = { static struct clk usbhost_ick = {
/* Handles both L3 and L4 clocks */ /* Handles both L3 and L4 clocks */
.name = "usbhost_ick", .name = "usbhost_ick",
.ops = &clkops_omap2_dflt_wait, .ops = &clkops_omap3430es2_dss_usbhost_wait,
.parent = &l4_ick, .parent = &l4_ick,
.init = &omap2_init_clk_clkdm, .init = &omap2_init_clk_clkdm,
.enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
......
...@@ -29,9 +29,9 @@ ...@@ -29,9 +29,9 @@
* These registers appear once per CM module. * These registers appear once per CM module.
*/ */
#define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) #define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
#define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) #define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
#define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) #define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
......
...@@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void) ...@@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void)
return v; return v;
} }
void __init omap2_init_common_hw(struct omap_sdrc_params *sp) void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{ {
omap2_mux_init(); omap2_mux_init();
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */ #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
pwrdm_init(powerdomains_omap); pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init(); omap2_clk_init();
omap2_sdrc_init(sp); omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc(); _omap2_init_reprogram_sdrc();
#endif #endif
gpmc_init(); gpmc_init();
......
...@@ -119,6 +119,7 @@ static int twl_mmc_late_init(struct device *dev) ...@@ -119,6 +119,7 @@ static int twl_mmc_late_init(struct device *dev)
if (i != 0) if (i != 0)
break; break;
ret = PTR_ERR(reg); ret = PTR_ERR(reg);
hsmmc[i].vcc = NULL;
goto err; goto err;
} }
hsmmc[i].vcc = reg; hsmmc[i].vcc = reg;
...@@ -165,8 +166,13 @@ static int twl_mmc_late_init(struct device *dev) ...@@ -165,8 +166,13 @@ static int twl_mmc_late_init(struct device *dev)
static void twl_mmc_cleanup(struct device *dev) static void twl_mmc_cleanup(struct device *dev)
{ {
struct omap_mmc_platform_data *mmc = dev->platform_data; struct omap_mmc_platform_data *mmc = dev->platform_data;
int i;
gpio_free(mmc->slots[0].switch_pin); gpio_free(mmc->slots[0].switch_pin);
for(i = 0; i < ARRAY_SIZE(hsmmc); i++) {
regulator_put(hsmmc[i].vcc);
regulator_put(hsmmc[i].vcc_aux);
}
} }
#ifdef CONFIG_PM #ifdef CONFIG_PM
......
...@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c, ...@@ -486,6 +486,12 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
}; };
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) #define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
......
...@@ -11,9 +11,6 @@ ...@@ -11,9 +11,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_PM_H #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
#define __ARCH_ARM_MACH_OMAP2_PM_H #define __ARCH_ARM_MACH_OMAP2_PM_H
extern int omap2_pm_init(void);
extern int omap3_pm_init(void);
#ifdef CONFIG_PM_DEBUG #ifdef CONFIG_PM_DEBUG
extern void omap2_pm_dump(int mode, int resume, unsigned int us); extern void omap2_pm_dump(int mode, int resume, unsigned int us);
extern int omap2_pm_debug; extern int omap2_pm_debug;
......
...@@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void) ...@@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void)
WKUP_MOD, PM_WKEN); WKUP_MOD, PM_WKEN);
} }
int __init omap2_pm_init(void) static int __init omap2_pm_init(void)
{ {
u32 l; u32 l;
......
...@@ -39,7 +39,9 @@ ...@@ -39,7 +39,9 @@
struct power_state { struct power_state {
struct powerdomain *pwrdm; struct powerdomain *pwrdm;
u32 next_state; u32 next_state;
#ifdef CONFIG_SUSPEND
u32 saved_state; u32 saved_state;
#endif
struct list_head node; struct list_head node;
}; };
...@@ -293,6 +295,9 @@ static void omap3_pm_idle(void) ...@@ -293,6 +295,9 @@ static void omap3_pm_idle(void)
local_irq_enable(); local_irq_enable();
} }
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state;
static int omap3_pm_prepare(void) static int omap3_pm_prepare(void)
{ {
disable_hlt(); disable_hlt();
...@@ -321,7 +326,6 @@ static int omap3_pm_suspend(void) ...@@ -321,7 +326,6 @@ static int omap3_pm_suspend(void)
restore: restore:
/* Restore next_pwrsts */ /* Restore next_pwrsts */
list_for_each_entry(pwrst, &pwrst_list, node) { list_for_each_entry(pwrst, &pwrst_list, node) {
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
state = pwrdm_read_prev_pwrst(pwrst->pwrdm); state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
if (state > pwrst->next_state) { if (state > pwrst->next_state) {
printk(KERN_INFO "Powerdomain (%s) didn't enter " printk(KERN_INFO "Powerdomain (%s) didn't enter "
...@@ -329,6 +333,7 @@ static int omap3_pm_suspend(void) ...@@ -329,6 +333,7 @@ static int omap3_pm_suspend(void)
pwrst->pwrdm->name, pwrst->next_state); pwrst->pwrdm->name, pwrst->next_state);
ret = -1; ret = -1;
} }
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
} }
if (ret) if (ret)
printk(KERN_ERR "Could not enter target state in pm_suspend\n"); printk(KERN_ERR "Could not enter target state in pm_suspend\n");
...@@ -339,11 +344,11 @@ static int omap3_pm_suspend(void) ...@@ -339,11 +344,11 @@ static int omap3_pm_suspend(void)
return ret; return ret;
} }
static int omap3_pm_enter(suspend_state_t state) static int omap3_pm_enter(suspend_state_t unused)
{ {
int ret = 0; int ret = 0;
switch (state) { switch (suspend_state) {
case PM_SUSPEND_STANDBY: case PM_SUSPEND_STANDBY:
case PM_SUSPEND_MEM: case PM_SUSPEND_MEM:
ret = omap3_pm_suspend(); ret = omap3_pm_suspend();
...@@ -360,12 +365,30 @@ static void omap3_pm_finish(void) ...@@ -360,12 +365,30 @@ static void omap3_pm_finish(void)
enable_hlt(); enable_hlt();
} }
/* Hooks to enable / disable UART interrupts during suspend */
static int omap3_pm_begin(suspend_state_t state)
{
suspend_state = state;
omap_uart_enable_irqs(0);
return 0;
}
static void omap3_pm_end(void)
{
suspend_state = PM_SUSPEND_ON;
omap_uart_enable_irqs(1);
return;
}
static struct platform_suspend_ops omap_pm_ops = { static struct platform_suspend_ops omap_pm_ops = {
.begin = omap3_pm_begin,
.end = omap3_pm_end,
.prepare = omap3_pm_prepare, .prepare = omap3_pm_prepare,
.enter = omap3_pm_enter, .enter = omap3_pm_enter,
.finish = omap3_pm_finish, .finish = omap3_pm_finish,
.valid = suspend_valid_only_mem, .valid = suspend_valid_only_mem,
}; };
#endif /* CONFIG_SUSPEND */
/** /**
...@@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void) ...@@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void)
/* Clear any pending PRCM interrupts */ /* Clear any pending PRCM interrupts */
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
/* Don't attach IVA interrupts */
prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
/* Clear any pending 'reset' flags */
prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
/* Clear any pending PRCM interrupts */
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
omap3_iva_idle(); omap3_iva_idle();
omap3_d2d_idle(); omap3_d2d_idle();
} }
...@@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm) ...@@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
return 0; return 0;
} }
int __init omap3_pm_init(void) static int __init omap3_pm_init(void)
{ {
struct power_state *pwrst, *tmp; struct power_state *pwrst, *tmp;
int ret; int ret;
...@@ -692,7 +733,9 @@ int __init omap3_pm_init(void) ...@@ -692,7 +733,9 @@ int __init omap3_pm_init(void)
_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
omap34xx_cpu_suspend_sz); omap34xx_cpu_suspend_sz);
#ifdef CONFIG_SUSPEND
suspend_set_ops(&omap_pm_ops); suspend_set_ops(&omap_pm_ops);
#endif /* CONFIG_SUSPEND */
pm_idle = omap3_pm_idle; pm_idle = omap3_pm_idle;
......
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/delay.h>
#include <mach/common.h> #include <mach/common.h>
#include <mach/prcm.h> #include <mach/prcm.h>
...@@ -28,6 +29,8 @@ ...@@ -28,6 +29,8 @@
static void __iomem *prm_base; static void __iomem *prm_base;
static void __iomem *cm_base; static void __iomem *cm_base;
#define MAX_MODULE_ENABLE_WAIT 100000
u32 omap_prcm_get_reset_sources(void) u32 omap_prcm_get_reset_sources(void)
{ {
/* XXX This presumably needs modification for 34XX */ /* XXX This presumably needs modification for 34XX */
...@@ -120,6 +123,46 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) ...@@ -120,6 +123,46 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
} }
EXPORT_SYMBOL(cm_rmw_mod_reg_bits); EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
/**
* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
* @reg: physical address of module IDLEST register
* @mask: value to mask against to determine if the module is active
* @name: name of the clock (for printk)
*
* Returns 1 if the module indicated readiness in time, or 0 if it
* failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
*/
int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
{
int i = 0;
int ena = 0;
/*
* 24xx uses 0 to indicate not ready, and 1 to indicate ready.
* 34xx reverses this, just to keep us on our toes
*/
if (cpu_is_omap24xx())
ena = mask;
else if (cpu_is_omap34xx())
ena = 0;
else
BUG();
/* Wait for lock */
while (((__raw_readl(reg) & mask) != ena) &&
(i++ < MAX_MODULE_ENABLE_WAIT))
udelay(1);
if (i < MAX_MODULE_ENABLE_WAIT)
pr_debug("cm: Module associated with clock %s ready after %d "
"loops\n", name, i);
else
pr_err("cm: Module associated with clock %s didn't enable in "
"%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
};
void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
{ {
prm_base = omap2_globals->prm; prm_base = omap2_globals->prm;
......
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#include <mach/sdrc.h> #include <mach/sdrc.h>
#include "sdrc.h" #include "sdrc.h"
static struct omap_sdrc_params *sdrc_init_params; static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
void __iomem *omap2_sdrc_base; void __iomem *omap2_sdrc_base;
void __iomem *omap2_sms_base; void __iomem *omap2_sms_base;
...@@ -45,33 +45,49 @@ void __iomem *omap2_sms_base; ...@@ -45,33 +45,49 @@ void __iomem *omap2_sms_base;
/** /**
* omap2_sdrc_get_params - return SDRC register values for a given clock rate * omap2_sdrc_get_params - return SDRC register values for a given clock rate
* @r: SDRC clock rate (in Hz) * @r: SDRC clock rate (in Hz)
* @sdrc_cs0: chip select 0 ram timings **
* @sdrc_cs1: chip select 1 ram timings **
* *
* Return pre-calculated values for the SDRC_ACTIM_CTRLA, * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
* SDRC clock rate 'r'. These parameters control various timing * structs,for a given SDRC clock rate 'r'.
* delays in the SDRAM controller that are expressed in terms of the * These parameters control various timing delays in the SDRAM controller
* number of SDRC clock cycles to wait; hence the clock rate * that are expressed in terms of the number of SDRC clock cycles to
* dependency. Note that sdrc_init_params must be sorted rate * wait; hence the clock rate dependency.
* descending. Also assumes that both chip-selects use the same *
* timing parameters. Returns a struct omap_sdrc_params * upon * Supports 2 different timing parameters for both chip selects.
* success, or NULL upon failure. *
* Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
* Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
* as sdrc_init_params_cs_0.
*
* Fills in the struct omap_sdrc_params * for each chip select.
* Returns 0 upon success or -1 upon failure.
*/ */
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r) int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1)
{ {
struct omap_sdrc_params *sp; struct omap_sdrc_params *sp0, *sp1;
if (!sdrc_init_params) if (!sdrc_init_params_cs0)
return NULL; return -1;
sp = sdrc_init_params; sp0 = sdrc_init_params_cs0;
sp1 = sdrc_init_params_cs1;
while (sp->rate && sp->rate != r) while (sp0->rate && sp0->rate != r) {
sp++; sp0++;
if (sdrc_init_params_cs1)
sp1++;
}
if (!sp->rate) if (!sp0->rate)
return NULL; return -1;
return sp; *sdrc_cs0 = sp0;
*sdrc_cs1 = sp1;
return 0;
} }
...@@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) ...@@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
/** /**
* omap2_sdrc_init - initialize SMS, SDRC devices on boot * omap2_sdrc_init - initialize SMS, SDRC devices on boot
* @sp: pointer to a null-terminated list of struct omap_sdrc_params * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
* Support for 2 chip selects timings
* *
* Turn on smart idle modes for SDRAM scheduler and controller. * Turn on smart idle modes for SDRAM scheduler and controller.
* Program a known-good configuration for the SDRC to deal with buggy * Program a known-good configuration for the SDRC to deal with buggy
* bootloaders. * bootloaders.
*/ */
void __init omap2_sdrc_init(struct omap_sdrc_params *sp) void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{ {
u32 l; u32 l;
...@@ -103,11 +121,15 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp) ...@@ -103,11 +121,15 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
l |= (0x2 << 3); l |= (0x2 << 3);
sdrc_write_reg(l, SDRC_SYSCONFIG); sdrc_write_reg(l, SDRC_SYSCONFIG);
sdrc_init_params = sp; sdrc_init_params_cs0 = sdrc_cs0;
sdrc_init_params_cs1 = sdrc_cs1;
/* XXX Enable SRFRONIDLEREQ here also? */ /* XXX Enable SRFRONIDLEREQ here also? */
/*
* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
* can cause random memory corruption
*/
l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
(1 << SDRC_POWER_PWDENA_SHIFT) |
(1 << SDRC_POWER_PAGEPOLICY_SHIFT); (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
sdrc_write_reg(l, SDRC_POWER); sdrc_write_reg(l, SDRC_POWER);
} }
...@@ -54,6 +54,7 @@ struct omap_uart_state { ...@@ -54,6 +54,7 @@ struct omap_uart_state {
struct plat_serial8250_port *p; struct plat_serial8250_port *p;
struct list_head node; struct list_head node;
struct platform_device pdev;
#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
int context_valid; int context_valid;
...@@ -68,10 +69,9 @@ struct omap_uart_state { ...@@ -68,10 +69,9 @@ struct omap_uart_state {
#endif #endif
}; };
static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
static LIST_HEAD(uart_list); static LIST_HEAD(uart_list);
static struct plat_serial8250_port serial_platform_data[] = { static struct plat_serial8250_port serial_platform_data0[] = {
{ {
.membase = IO_ADDRESS(OMAP_UART1_BASE), .membase = IO_ADDRESS(OMAP_UART1_BASE),
.mapbase = OMAP_UART1_BASE, .mapbase = OMAP_UART1_BASE,
...@@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = { ...@@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
.regshift = 2, .regshift = 2,
.uartclk = OMAP24XX_BASE_BAUD * 16, .uartclk = OMAP24XX_BASE_BAUD * 16,
}, { }, {
.flags = 0
}
};
static struct plat_serial8250_port serial_platform_data1[] = {
{
.membase = IO_ADDRESS(OMAP_UART2_BASE), .membase = IO_ADDRESS(OMAP_UART2_BASE),
.mapbase = OMAP_UART2_BASE, .mapbase = OMAP_UART2_BASE,
.irq = 73, .irq = 73,
...@@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = { ...@@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
.regshift = 2, .regshift = 2,
.uartclk = OMAP24XX_BASE_BAUD * 16, .uartclk = OMAP24XX_BASE_BAUD * 16,
}, { }, {
.flags = 0
}
};
static struct plat_serial8250_port serial_platform_data2[] = {
{
.membase = IO_ADDRESS(OMAP_UART3_BASE), .membase = IO_ADDRESS(OMAP_UART3_BASE),
.mapbase = OMAP_UART3_BASE, .mapbase = OMAP_UART3_BASE,
.irq = 74, .irq = 74,
...@@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) ...@@ -217,6 +229,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
clk_disable(uart->fck); clk_disable(uart->fck);
} }
static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
{
/* Set wake-enable bit */
if (uart->wk_en && uart->wk_mask) {
u32 v = __raw_readl(uart->wk_en);
v |= uart->wk_mask;
__raw_writel(v, uart->wk_en);
}
/* Ensure IOPAD wake-enables are set */
if (cpu_is_omap34xx() && uart->padconf) {
u16 v = omap_ctrl_readw(uart->padconf);
v |= OMAP3_PADCONF_WAKEUPENABLE0;
omap_ctrl_writew(v, uart->padconf);
}
}
static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
{
/* Clear wake-enable bit */
if (uart->wk_en && uart->wk_mask) {
u32 v = __raw_readl(uart->wk_en);
v &= ~uart->wk_mask;
__raw_writel(v, uart->wk_en);
}
/* Ensure IOPAD wake-enables are cleared */
if (cpu_is_omap34xx() && uart->padconf) {
u16 v = omap_ctrl_readw(uart->padconf);
v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
omap_ctrl_writew(v, uart->padconf);
}
}
static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
int enable) int enable)
{ {
...@@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart) ...@@ -246,6 +292,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
static void omap_uart_allow_sleep(struct omap_uart_state *uart) static void omap_uart_allow_sleep(struct omap_uart_state *uart)
{ {
if (device_may_wakeup(&uart->pdev.dev))
omap_uart_enable_wakeup(uart);
else
omap_uart_disable_wakeup(uart);
if (!uart->clocked) if (!uart->clocked)
return; return;
...@@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num) ...@@ -292,7 +343,6 @@ void omap_uart_resume_idle(int num)
/* Check for normal UART wakeup */ /* Check for normal UART wakeup */
if (__raw_readl(uart->wk_st) & uart->wk_mask) if (__raw_readl(uart->wk_st) & uart->wk_mask)
omap_uart_block_sleep(uart); omap_uart_block_sleep(uart);
return; return;
} }
} }
...@@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) ...@@ -346,16 +396,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
return IRQ_NONE; return IRQ_NONE;
} }
static u32 sleep_timeout = DEFAULT_TIMEOUT;
static void omap_uart_idle_init(struct omap_uart_state *uart) static void omap_uart_idle_init(struct omap_uart_state *uart)
{ {
u32 v;
struct plat_serial8250_port *p = uart->p; struct plat_serial8250_port *p = uart->p;
int ret; int ret;
uart->can_sleep = 0; uart->can_sleep = 0;
uart->timeout = sleep_timeout; uart->timeout = DEFAULT_TIMEOUT;
setup_timer(&uart->timer, omap_uart_idle_timer, setup_timer(&uart->timer, omap_uart_idle_timer,
(unsigned long) uart); (unsigned long) uart);
mod_timer(&uart->timer, jiffies + uart->timeout); mod_timer(&uart->timer, jiffies + uart->timeout);
...@@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) ...@@ -413,76 +460,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
uart->padconf = 0; uart->padconf = 0;
} }
/* Set wake-enable bit */
if (uart->wk_en && uart->wk_mask) {
v = __raw_readl(uart->wk_en);
v |= uart->wk_mask;
__raw_writel(v, uart->wk_en);
}
/* Ensure IOPAD wake-enables are set */
if (cpu_is_omap34xx() && uart->padconf) {
u16 v;
v = omap_ctrl_readw(uart->padconf);
v |= OMAP3_PADCONF_WAKEUPENABLE0;
omap_ctrl_writew(v, uart->padconf);
}
p->flags |= UPF_SHARE_IRQ; p->flags |= UPF_SHARE_IRQ;
ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
"serial idle", (void *)uart); "serial idle", (void *)uart);
WARN_ON(ret); WARN_ON(ret);
} }
static ssize_t sleep_timeout_show(struct kobject *kobj, void omap_uart_enable_irqs(int enable)
struct kobj_attribute *attr, {
int ret;
struct omap_uart_state *uart;
list_for_each_entry(uart, &uart_list, node) {
if (enable)
ret = request_irq(uart->p->irq, omap_uart_interrupt,
IRQF_SHARED, "serial idle", (void *)uart);
else
free_irq(uart->p->irq, (void *)uart);
}
}
static ssize_t sleep_timeout_show(struct device *dev,
struct device_attribute *attr,
char *buf) char *buf)
{ {
return sprintf(buf, "%u\n", sleep_timeout / HZ); struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct omap_uart_state *uart = container_of(pdev,
struct omap_uart_state, pdev);
return sprintf(buf, "%u\n", uart->timeout / HZ);
} }
static ssize_t sleep_timeout_store(struct kobject *kobj, static ssize_t sleep_timeout_store(struct device *dev,
struct kobj_attribute *attr, struct device_attribute *attr,
const char *buf, size_t n) const char *buf, size_t n)
{ {
struct omap_uart_state *uart; struct platform_device *pdev = container_of(dev,
struct platform_device, dev);
struct omap_uart_state *uart = container_of(pdev,
struct omap_uart_state, pdev);
unsigned int value; unsigned int value;
if (sscanf(buf, "%u", &value) != 1) { if (sscanf(buf, "%u", &value) != 1) {
printk(KERN_ERR "sleep_timeout_store: Invalid value\n"); printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
return -EINVAL; return -EINVAL;
} }
sleep_timeout = value * HZ;
list_for_each_entry(uart, &uart_list, node) { uart->timeout = value * HZ;
uart->timeout = sleep_timeout; if (uart->timeout)
if (uart->timeout) mod_timer(&uart->timer, jiffies + uart->timeout);
mod_timer(&uart->timer, jiffies + uart->timeout); else
else /* A zero value means disable timeout feature */
/* A zero value means disable timeout feature */ omap_uart_block_sleep(uart);
omap_uart_block_sleep(uart);
}
return n; return n;
} }
static struct kobj_attribute sleep_timeout_attr = DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
__ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store); #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
#else #else
static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
#define DEV_CREATE_FILE(dev, attr)
#endif /* CONFIG_PM */ #endif /* CONFIG_PM */
static struct platform_device serial_device = { static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
.name = "serial8250", {
.id = PLAT8250_DEV_PLATFORM, .pdev = {
.dev = { .name = "serial8250",
.platform_data = serial_platform_data, .id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data0,
},
},
}, {
.pdev = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM1,
.dev = {
.platform_data = serial_platform_data1,
},
},
}, {
.pdev = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM2,
.dev = {
.platform_data = serial_platform_data2,
},
},
}, },
}; };
void __init omap_serial_init(void) void __init omap_serial_init(void)
{ {
int i, err; int i;
const struct omap_uart_config *info; const struct omap_uart_config *info;
char name[16]; char name[16];
...@@ -496,14 +568,12 @@ void __init omap_serial_init(void) ...@@ -496,14 +568,12 @@ void __init omap_serial_init(void)
if (info == NULL) if (info == NULL)
return; return;
if (cpu_is_omap44xx()) {
for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
serial_platform_data[i].irq += 32;
}
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
struct plat_serial8250_port *p = serial_platform_data + i;
struct omap_uart_state *uart = &omap_uart[i]; struct omap_uart_state *uart = &omap_uart[i];
struct platform_device *pdev = &uart->pdev;
struct device *dev = &pdev->dev;
struct plat_serial8250_port *p = dev->platform_data;
if (!(info->enabled_uarts & (1 << i))) { if (!(info->enabled_uarts & (1 << i))) {
p->membase = NULL; p->membase = NULL;
...@@ -531,20 +601,21 @@ void __init omap_serial_init(void) ...@@ -531,20 +601,21 @@ void __init omap_serial_init(void)
uart->num = i; uart->num = i;
p->private_data = uart; p->private_data = uart;
uart->p = p; uart->p = p;
list_add(&uart->node, &uart_list); list_add_tail(&uart->node, &uart_list);
if (cpu_is_omap44xx())
p->irq += 32;
omap_uart_enable_clocks(uart); omap_uart_enable_clocks(uart);
omap_uart_reset(uart); omap_uart_reset(uart);
omap_uart_idle_init(uart); omap_uart_idle_init(uart);
}
err = platform_device_register(&serial_device);
#ifdef CONFIG_PM
if (!err)
err = sysfs_create_file(&serial_device.dev.kobj,
&sleep_timeout_attr.attr);
#endif
if (WARN_ON(platform_device_register(pdev)))
continue;
if ((cpu_is_omap34xx() && uart->padconf) ||
(uart->wk_en && uart->wk_mask)) {
device_init_wakeup(dev, true);
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
}
}
} }
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
.text .text
/* r4 parameters */ /* r1 parameters */
#define SDRC_NO_UNLOCK_DLL 0x0 #define SDRC_NO_UNLOCK_DLL 0x0
#define SDRC_UNLOCK_DLL 0x1 #define SDRC_UNLOCK_DLL 0x1
...@@ -58,7 +58,6 @@ ...@@ -58,7 +58,6 @@
/* SDRC_POWER bit settings */ /* SDRC_POWER bit settings */
#define SRFRONIDLEREQ_MASK 0x40 #define SRFRONIDLEREQ_MASK 0x40
#define PWDENA_MASK 0x4
/* CM_IDLEST1_CORE bit settings */ /* CM_IDLEST1_CORE bit settings */
#define ST_SDRC_MASK 0x2 #define ST_SDRC_MASK 0x2
...@@ -71,41 +70,72 @@ ...@@ -71,41 +70,72 @@
/* /*
* omap3_sram_configure_core_dpll - change DPLL3 M2 divider * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
* r0 = new SDRC_RFR_CTRL register contents *
* r1 = new SDRC_ACTIM_CTRLA register contents * Params passed in registers:
* r2 = new SDRC_ACTIM_CTRLB register contents * r0 = new M2 divider setting (only 1 and 2 supported right now)
* r3 = new M2 divider setting (only 1 and 2 supported right now) * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
* SDRC rates < 83MHz * SDRC rates < 83MHz
* r5 = number of MPU cycles to wait for SDRC to stabilize after * r2 = number of MPU cycles to wait for SDRC to stabilize after
* reprogramming the SDRC when switching to a slower MPU speed * reprogramming the SDRC when switching to a slower MPU speed
* r6 = new SDRC_MR_0 register value * r3 = increasing SDRC rate? (1 = yes, 0 = no)
* r7 = increasing SDRC rate? (1 = yes, 0 = no) *
* Params passed via the stack. The needed params will be copied in SRAM
* before use by the code in SRAM (SDRAM is not accessible during SDRC
* reconfiguration):
* new SDRC_RFR_CTRL_0 register contents
* new SDRC_ACTIM_CTRL_A_0 register contents
* new SDRC_ACTIM_CTRL_B_0 register contents
* new SDRC_MR_0 register value
* new SDRC_RFR_CTRL_1 register contents
* new SDRC_ACTIM_CTRL_A_1 register contents
* new SDRC_ACTIM_CTRL_B_1 register contents
* new SDRC_MR_1 register value
* *
* If the param SDRC_RFR_CTRL_1 is 0, the parameters
* are not programmed into the SDRC CS1 registers
*/ */
ENTRY(omap3_sram_configure_core_dpll) ENTRY(omap3_sram_configure_core_dpll)
stmfd sp!, {r1-r12, lr} @ store regs to stack stmfd sp!, {r1-r12, lr} @ store regs to stack
ldr r4, [sp, #52] @ pull extra args off the stack
ldr r5, [sp, #56] @ load extra args from the stack @ pull the extra args off the stack
ldr r6, [sp, #60] @ load extra args from the stack @ and store them in SRAM
ldr r7, [sp, #64] @ load extra args from the stack ldr r4, [sp, #52]
str r4, omap_sdrc_rfr_ctrl_0_val
ldr r4, [sp, #56]
str r4, omap_sdrc_actim_ctrl_a_0_val
ldr r4, [sp, #60]
str r4, omap_sdrc_actim_ctrl_b_0_val
ldr r4, [sp, #64]
str r4, omap_sdrc_mr_0_val
ldr r4, [sp, #68]
str r4, omap_sdrc_rfr_ctrl_1_val
cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
beq skip_cs1_params @ do not use cs1 params
ldr r4, [sp, #72]
str r4, omap_sdrc_actim_ctrl_a_1_val
ldr r4, [sp, #76]
str r4, omap_sdrc_actim_ctrl_b_1_val
ldr r4, [sp, #80]
str r4, omap_sdrc_mr_1_val
skip_cs1_params:
dsb @ flush buffered writes to interconnect dsb @ flush buffered writes to interconnect
cmp r7, #1 @ if increasing SDRC clk rate,
cmp r3, #1 @ if increasing SDRC clk rate,
bleq configure_sdrc @ program the SDRC regs early (for RFR) bleq configure_sdrc @ program the SDRC regs early (for RFR)
cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
bleq unlock_dll bleq unlock_dll
blne lock_dll blne lock_dll
bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
bl configure_core_dpll @ change the DPLL3 M2 divider bl configure_core_dpll @ change the DPLL3 M2 divider
mov r12, r2
bl wait_clk_stable @ wait for SDRC to stabilize
bl enable_sdrc @ take SDRC out of idle bl enable_sdrc @ take SDRC out of idle
cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
bleq wait_dll_unlock bleq wait_dll_unlock
blne wait_dll_lock blne wait_dll_lock
cmp r7, #1 @ if increasing SDRC clk rate, cmp r3, #1 @ if increasing SDRC clk rate,
beq return_to_sdram @ return to SDRAM code, otherwise, beq return_to_sdram @ return to SDRAM code, otherwise,
bl configure_sdrc @ reprogram SDRC regs now bl configure_sdrc @ reprogram SDRC regs now
mov r12, r5
bl wait_clk_stable @ wait for SDRC to stabilize
return_to_sdram: return_to_sdram:
isb @ prevent speculative exec past here isb @ prevent speculative exec past here
mov r0, #0 @ return value mov r0, #0 @ return value
...@@ -113,7 +143,7 @@ return_to_sdram: ...@@ -113,7 +143,7 @@ return_to_sdram:
unlock_dll: unlock_dll:
ldr r11, omap3_sdrc_dlla_ctrl ldr r11, omap3_sdrc_dlla_ctrl
ldr r12, [r11] ldr r12, [r11]
and r12, r12, #FIXEDDELAY_MASK bic r12, r12, #FIXEDDELAY_MASK
orr r12, r12, #FIXEDDELAY_DEFAULT orr r12, r12, #FIXEDDELAY_DEFAULT
orr r12, r12, #DLLIDLE_MASK orr r12, r12, #DLLIDLE_MASK
str r12, [r11] @ (no OCP barrier needed) str r12, [r11] @ (no OCP barrier needed)
...@@ -129,7 +159,6 @@ sdram_in_selfrefresh: ...@@ -129,7 +159,6 @@ sdram_in_selfrefresh:
ldr r12, [r11] @ read the contents of SDRC_POWER ldr r12, [r11] @ read the contents of SDRC_POWER
mov r9, r12 @ keep a copy of SDRC_POWER bits mov r9, r12 @ keep a copy of SDRC_POWER bits
orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
bic r12, r12, #PWDENA_MASK @ clear PWDENA
str r12, [r11] @ write back to SDRC_POWER register str r12, [r11] @ write back to SDRC_POWER register
ldr r12, [r11] @ posted-write barrier for SDRC ldr r12, [r11] @ posted-write barrier for SDRC
idle_sdrc: idle_sdrc:
...@@ -149,7 +178,7 @@ configure_core_dpll: ...@@ -149,7 +178,7 @@ configure_core_dpll:
ldr r12, [r11] ldr r12, [r11]
ldr r10, core_m2_mask_val @ modify m2 for core dpll ldr r10, core_m2_mask_val @ modify m2 for core dpll
and r12, r12, r10 and r12, r12, r10
orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
str r12, [r11] str r12, [r11]
ldr r12, [r11] @ posted-write barrier for CM ldr r12, [r11] @ posted-write barrier for CM
bx lr bx lr
...@@ -187,15 +216,34 @@ wait_dll_unlock: ...@@ -187,15 +216,34 @@ wait_dll_unlock:
bne wait_dll_unlock bne wait_dll_unlock
bx lr bx lr
configure_sdrc: configure_sdrc:
ldr r11, omap3_sdrc_rfr_ctrl ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
str r0, [r11] ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
ldr r11, omap3_sdrc_actim_ctrla str r12, [r11] @ store
str r1, [r11] ldr r12, omap_sdrc_actim_ctrl_a_0_val
ldr r11, omap3_sdrc_actim_ctrlb ldr r11, omap3_sdrc_actim_ctrl_a_0
str r2, [r11] str r12, [r11]
ldr r12, omap_sdrc_actim_ctrl_b_0_val
ldr r11, omap3_sdrc_actim_ctrl_b_0
str r12, [r11]
ldr r12, omap_sdrc_mr_0_val
ldr r11, omap3_sdrc_mr_0 ldr r11, omap3_sdrc_mr_0
str r6, [r11] str r12, [r11]
ldr r6, [r11] @ posted-write barrier for SDRC ldr r12, omap_sdrc_rfr_ctrl_1_val
cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
beq skip_cs1_prog @ do not program cs1 params
ldr r11, omap3_sdrc_rfr_ctrl_1
str r12, [r11]
ldr r12, omap_sdrc_actim_ctrl_a_1_val
ldr r11, omap3_sdrc_actim_ctrl_a_1
str r12, [r11]
ldr r12, omap_sdrc_actim_ctrl_b_1_val
ldr r11, omap3_sdrc_actim_ctrl_b_1
str r12, [r11]
ldr r12, omap_sdrc_mr_1_val
ldr r11, omap3_sdrc_mr_1
str r12, [r11]
skip_cs1_prog:
ldr r12, [r11] @ posted-write barrier for SDRC
bx lr bx lr
omap3_sdrc_power: omap3_sdrc_power:
...@@ -206,14 +254,40 @@ omap3_cm_idlest1_core: ...@@ -206,14 +254,40 @@ omap3_cm_idlest1_core:
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
omap3_cm_iclken1_core: omap3_cm_iclken1_core:
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
omap3_sdrc_rfr_ctrl:
omap3_sdrc_rfr_ctrl_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0) .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
omap3_sdrc_actim_ctrla: omap3_sdrc_rfr_ctrl_1:
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
omap3_sdrc_actim_ctrl_a_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0) .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
omap3_sdrc_actim_ctrlb: omap3_sdrc_actim_ctrl_a_1:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
omap3_sdrc_actim_ctrl_b_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0) .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
omap3_sdrc_actim_ctrl_b_1:
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
omap3_sdrc_mr_0: omap3_sdrc_mr_0:
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0) .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
omap3_sdrc_mr_1:
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
omap_sdrc_rfr_ctrl_0_val:
.word 0xDEADBEEF
omap_sdrc_rfr_ctrl_1_val:
.word 0xDEADBEEF
omap_sdrc_actim_ctrl_a_0_val:
.word 0xDEADBEEF
omap_sdrc_actim_ctrl_a_1_val:
.word 0xDEADBEEF
omap_sdrc_actim_ctrl_b_0_val:
.word 0xDEADBEEF
omap_sdrc_actim_ctrl_b_1_val:
.word 0xDEADBEEF
omap_sdrc_mr_0_val:
.word 0xDEADBEEF
omap_sdrc_mr_1_val:
.word 0xDEADBEEF
omap3_sdrc_dlla_status: omap3_sdrc_dlla_status:
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS) .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
omap3_sdrc_dlla_ctrl: omap3_sdrc_dlla_ctrl:
...@@ -223,3 +297,4 @@ core_m2_mask_val: ...@@ -223,3 +297,4 @@ core_m2_mask_val:
ENTRY(omap3_sram_configure_core_dpll_sz) ENTRY(omap3_sram_configure_core_dpll_sz)
.word . - omap3_sram_configure_core_dpll .word . - omap3_sram_configure_core_dpll
...@@ -510,7 +510,7 @@ static struct db_chip db_chips[] __initdata = { ...@@ -510,7 +510,7 @@ static struct db_chip db_chips[] __initdata = {
} }
}; };
static void u300_init_check_chip(void) static void __init u300_init_check_chip(void)
{ {
u16 val; u16 val;
......
...@@ -120,6 +120,32 @@ void show_mem(void) ...@@ -120,6 +120,32 @@ void show_mem(void)
printk("%d pages swap cached\n", cached); printk("%d pages swap cached\n", cached);
} }
static void __init find_node_limits(int node, struct meminfo *mi,
unsigned long *min, unsigned long *max_low, unsigned long *max_high)
{
int i;
*min = -1UL;
*max_low = *max_high = 0;
for_each_nodebank(i, mi, node) {
struct membank *bank = &mi->bank[i];
unsigned long start, end;
start = bank_pfn_start(bank);
end = bank_pfn_end(bank);
if (*min > start)
*min = start;
if (*max_high < end)
*max_high = end;
if (bank->highmem)
continue;
if (*max_low < end)
*max_low = end;
}
}
/* /*
* FIXME: We really want to avoid allocating the bootmap bitmap * FIXME: We really want to avoid allocating the bootmap bitmap
* over the top of the initrd. Hopefully, this is located towards * over the top of the initrd. Hopefully, this is located towards
...@@ -210,40 +236,24 @@ static inline void map_memory_bank(struct membank *bank) ...@@ -210,40 +236,24 @@ static inline void map_memory_bank(struct membank *bank)
#endif #endif
} }
static unsigned long __init bootmem_init_node(int node, struct meminfo *mi) static void __init bootmem_init_node(int node, struct meminfo *mi,
unsigned long start_pfn, unsigned long end_pfn)
{ {
unsigned long start_pfn, end_pfn, boot_pfn; unsigned long boot_pfn;
unsigned int boot_pages; unsigned int boot_pages;
pg_data_t *pgdat; pg_data_t *pgdat;
int i; int i;
start_pfn = -1UL;
end_pfn = 0;
/* /*
* Calculate the pfn range, and map the memory banks for this node. * Map the memory banks for this node.
*/ */
for_each_nodebank(i, mi, node) { for_each_nodebank(i, mi, node) {
struct membank *bank = &mi->bank[i]; struct membank *bank = &mi->bank[i];
unsigned long start, end;
start = bank_pfn_start(bank); if (!bank->highmem)
end = bank_pfn_end(bank); map_memory_bank(bank);
if (start_pfn > start)
start_pfn = start;
if (end_pfn < end)
end_pfn = end;
map_memory_bank(bank);
} }
/*
* If there is no memory in this node, ignore it.
*/
if (end_pfn == 0)
return end_pfn;
/* /*
* Allocate the bootmem bitmap page. * Allocate the bootmem bitmap page.
*/ */
...@@ -260,7 +270,8 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi) ...@@ -260,7 +270,8 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
for_each_nodebank(i, mi, node) { for_each_nodebank(i, mi, node) {
struct membank *bank = &mi->bank[i]; struct membank *bank = &mi->bank[i];
free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank)); if (!bank->highmem)
free_bootmem_node(pgdat, bank_phys_start(bank), bank_phys_size(bank));
memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank)); memory_present(node, bank_pfn_start(bank), bank_pfn_end(bank));
} }
...@@ -269,8 +280,6 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi) ...@@ -269,8 +280,6 @@ static unsigned long __init bootmem_init_node(int node, struct meminfo *mi)
*/ */
reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT, reserve_bootmem_node(pgdat, boot_pfn << PAGE_SHIFT,
boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT); boot_pages << PAGE_SHIFT, BOOTMEM_DEFAULT);
return end_pfn;
} }
static void __init bootmem_reserve_initrd(int node) static void __init bootmem_reserve_initrd(int node)
...@@ -297,33 +306,39 @@ static void __init bootmem_reserve_initrd(int node) ...@@ -297,33 +306,39 @@ static void __init bootmem_reserve_initrd(int node)
static void __init bootmem_free_node(int node, struct meminfo *mi) static void __init bootmem_free_node(int node, struct meminfo *mi)
{ {
unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES]; unsigned long zone_size[MAX_NR_ZONES], zhole_size[MAX_NR_ZONES];
unsigned long start_pfn, end_pfn; unsigned long min, max_low, max_high;
pg_data_t *pgdat = NODE_DATA(node);
int i; int i;
start_pfn = pgdat->bdata->node_min_pfn; find_node_limits(node, mi, &min, &max_low, &max_high);
end_pfn = pgdat->bdata->node_low_pfn;
/* /*
* initialise the zones within this node. * initialise the zones within this node.
*/ */
memset(zone_size, 0, sizeof(zone_size)); memset(zone_size, 0, sizeof(zone_size));
memset(zhole_size, 0, sizeof(zhole_size));
/* /*
* The size of this node has already been determined. If we need * The size of this node has already been determined. If we need
* to do anything fancy with the allocation of this memory to the * to do anything fancy with the allocation of this memory to the
* zones, now is the time to do it. * zones, now is the time to do it.
*/ */
zone_size[0] = end_pfn - start_pfn; zone_size[0] = max_low - min;
#ifdef CONFIG_HIGHMEM
zone_size[ZONE_HIGHMEM] = max_high - max_low;
#endif
/* /*
* For each bank in this node, calculate the size of the holes. * For each bank in this node, calculate the size of the holes.
* holes = node_size - sum(bank_sizes_in_node) * holes = node_size - sum(bank_sizes_in_node)
*/ */
zhole_size[0] = zone_size[0]; memcpy(zhole_size, zone_size, sizeof(zhole_size));
for_each_nodebank(i, mi, node) for_each_nodebank(i, mi, node) {
zhole_size[0] -= bank_pfn_size(&mi->bank[i]); int idx = 0;
#ifdef CONFIG_HIGHMEM
if (mi->bank[i].highmem)
idx = ZONE_HIGHMEM;
#endif
zhole_size[idx] -= bank_pfn_size(&mi->bank[i]);
}
/* /*
* Adjust the sizes according to any special requirements for * Adjust the sizes according to any special requirements for
...@@ -331,13 +346,13 @@ static void __init bootmem_free_node(int node, struct meminfo *mi) ...@@ -331,13 +346,13 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
*/ */
arch_adjust_zones(node, zone_size, zhole_size); arch_adjust_zones(node, zone_size, zhole_size);
free_area_init_node(node, zone_size, start_pfn, zhole_size); free_area_init_node(node, zone_size, min, zhole_size);
} }
void __init bootmem_init(void) void __init bootmem_init(void)
{ {
struct meminfo *mi = &meminfo; struct meminfo *mi = &meminfo;
unsigned long memend_pfn = 0; unsigned long min, max_low, max_high;
int node, initrd_node; int node, initrd_node;
/* /*
...@@ -345,11 +360,29 @@ void __init bootmem_init(void) ...@@ -345,11 +360,29 @@ void __init bootmem_init(void)
*/ */
initrd_node = check_initrd(mi); initrd_node = check_initrd(mi);
max_low = max_high = 0;
/* /*
* Run through each node initialising the bootmem allocator. * Run through each node initialising the bootmem allocator.
*/ */
for_each_node(node) { for_each_node(node) {
unsigned long end_pfn = bootmem_init_node(node, mi); unsigned long node_low, node_high;
find_node_limits(node, mi, &min, &node_low, &node_high);
if (node_low > max_low)
max_low = node_low;
if (node_high > max_high)
max_high = node_high;
/*
* If there is no memory in this node, ignore it.
* (We can't have nodes which have no lowmem)
*/
if (node_low == 0)
continue;
bootmem_init_node(node, mi, min, node_low);
/* /*
* Reserve any special node zero regions. * Reserve any special node zero regions.
...@@ -362,12 +395,6 @@ void __init bootmem_init(void) ...@@ -362,12 +395,6 @@ void __init bootmem_init(void)
*/ */
if (node == initrd_node) if (node == initrd_node)
bootmem_reserve_initrd(node); bootmem_reserve_initrd(node);
/*
* Remember the highest memory PFN.
*/
if (end_pfn > memend_pfn)
memend_pfn = end_pfn;
} }
/* /*
...@@ -383,7 +410,7 @@ void __init bootmem_init(void) ...@@ -383,7 +410,7 @@ void __init bootmem_init(void)
for_each_node(node) for_each_node(node)
bootmem_free_node(node, mi); bootmem_free_node(node, mi);
high_memory = __va((memend_pfn << PAGE_SHIFT) - 1) + 1; high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
/* /*
* This doesn't seem to be used by the Linux memory manager any * This doesn't seem to be used by the Linux memory manager any
...@@ -393,7 +420,8 @@ void __init bootmem_init(void) ...@@ -393,7 +420,8 @@ void __init bootmem_init(void)
* Note: max_low_pfn and max_pfn reflect the number of _pages_ in * Note: max_low_pfn and max_pfn reflect the number of _pages_ in
* the system, not the maximum PFN. * the system, not the maximum PFN.
*/ */
max_pfn = max_low_pfn = memend_pfn - PHYS_PFN_OFFSET; max_low_pfn = max_low - PHYS_PFN_OFFSET;
max_pfn = max_high - PHYS_PFN_OFFSET;
} }
static inline int free_area(unsigned long pfn, unsigned long end, char *s) static inline int free_area(unsigned long pfn, unsigned long end, char *s)
......
...@@ -687,13 +687,19 @@ __early_param("vmalloc=", early_vmalloc); ...@@ -687,13 +687,19 @@ __early_param("vmalloc=", early_vmalloc);
static void __init sanity_check_meminfo(void) static void __init sanity_check_meminfo(void)
{ {
int i, j; int i, j, highmem = 0;
for (i = 0, j = 0; i < meminfo.nr_banks; i++) { for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
struct membank *bank = &meminfo.bank[j]; struct membank *bank = &meminfo.bank[j];
*bank = meminfo.bank[i]; *bank = meminfo.bank[i];
#ifdef CONFIG_HIGHMEM #ifdef CONFIG_HIGHMEM
if (__va(bank->start) > VMALLOC_MIN ||
__va(bank->start) < (void *)PAGE_OFFSET)
highmem = 1;
bank->highmem = highmem;
/* /*
* Split those memory banks which are partially overlapping * Split those memory banks which are partially overlapping
* the vmalloc area greatly simplifying things later. * the vmalloc area greatly simplifying things later.
...@@ -714,6 +720,7 @@ static void __init sanity_check_meminfo(void) ...@@ -714,6 +720,7 @@ static void __init sanity_check_meminfo(void)
i++; i++;
bank[1].size -= VMALLOC_MIN - __va(bank->start); bank[1].size -= VMALLOC_MIN - __va(bank->start);
bank[1].start = __pa(VMALLOC_MIN - 1) + 1; bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
bank[1].highmem = highmem = 1;
j++; j++;
} }
bank->size = VMALLOC_MIN - __va(bank->start); bank->size = VMALLOC_MIN - __va(bank->start);
......
...@@ -78,10 +78,10 @@ static int omap_target(struct cpufreq_policy *policy, ...@@ -78,10 +78,10 @@ static int omap_target(struct cpufreq_policy *policy,
/* Ensure desired rate is within allowed range. Some govenors /* Ensure desired rate is within allowed range. Some govenors
* (ondemand) will just pass target_freq=0 to get the minimum. */ * (ondemand) will just pass target_freq=0 to get the minimum. */
if (target_freq < policy->cpuinfo.min_freq) if (target_freq < policy->min)
target_freq = policy->cpuinfo.min_freq; target_freq = policy->min;
if (target_freq > policy->cpuinfo.max_freq) if (target_freq > policy->max)
target_freq = policy->cpuinfo.max_freq; target_freq = policy->max;
freqs.old = omap_getspeed(0); freqs.old = omap_getspeed(0);
freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000; freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
......
...@@ -946,7 +946,9 @@ void omap_start_dma(int lch) ...@@ -946,7 +946,9 @@ void omap_start_dma(int lch)
cur_lch = next_lch; cur_lch = next_lch;
} while (next_lch != -1); } while (next_lch != -1);
} else if (cpu_class_is_omap2()) { } else if (cpu_is_omap242x() ||
(cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
/* Errata: Need to write lch even if not using chaining */ /* Errata: Need to write lch even if not using chaining */
dma_write(lch, CLNK_CTRL(lch)); dma_write(lch, CLNK_CTRL(lch));
} }
......
...@@ -476,14 +476,12 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) ...@@ -476,14 +476,12 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
__raw_writel(l, reg); __raw_writel(l, reg);
} }
static int __omap_get_gpio_datain(int gpio) static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{ {
struct gpio_bank *bank;
void __iomem *reg; void __iomem *reg;
if (check_gpio(gpio) < 0) if (check_gpio(gpio) < 0)
return -EINVAL; return -EINVAL;
bank = get_gpio_bank(gpio);
reg = bank->base; reg = bank->base;
switch (bank->method) { switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1 #ifdef CONFIG_ARCH_OMAP1
...@@ -524,6 +522,53 @@ static int __omap_get_gpio_datain(int gpio) ...@@ -524,6 +522,53 @@ static int __omap_get_gpio_datain(int gpio)
& (1 << get_gpio_index(gpio))) != 0; & (1 << get_gpio_index(gpio))) != 0;
} }
static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
{
void __iomem *reg;
if (check_gpio(gpio) < 0)
return -EINVAL;
reg = bank->base;
switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
case METHOD_MPUIO:
reg += OMAP_MPUIO_OUTPUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DATA_OUTPUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP16XX
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_DATAOUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP730
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DATA_OUTPUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP850
case METHOD_GPIO_850:
reg += OMAP850_GPIO_DATA_OUTPUT;
break;
#endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
defined(CONFIG_ARCH_OMAP4)
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_DATAOUT;
break;
#endif
default:
return -EINVAL;
}
return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
}
#define MOD_REG_BIT(reg, bit_mask, set) \ #define MOD_REG_BIT(reg, bit_mask, set) \
do { \ do { \
int l = __raw_readl(base + reg); \ int l = __raw_readl(base + reg); \
...@@ -1189,6 +1234,7 @@ static void gpio_mask_irq(unsigned int irq) ...@@ -1189,6 +1234,7 @@ static void gpio_mask_irq(unsigned int irq)
struct gpio_bank *bank = get_irq_chip_data(irq); struct gpio_bank *bank = get_irq_chip_data(irq);
_set_gpio_irqenable(bank, gpio, 0); _set_gpio_irqenable(bank, gpio, 0);
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
} }
static void gpio_unmask_irq(unsigned int irq) static void gpio_unmask_irq(unsigned int irq)
...@@ -1196,6 +1242,11 @@ static void gpio_unmask_irq(unsigned int irq) ...@@ -1196,6 +1242,11 @@ static void gpio_unmask_irq(unsigned int irq)
unsigned int gpio = irq - IH_GPIO_BASE; unsigned int gpio = irq - IH_GPIO_BASE;
struct gpio_bank *bank = get_irq_chip_data(irq); struct gpio_bank *bank = get_irq_chip_data(irq);
unsigned int irq_mask = 1 << get_gpio_index(gpio); unsigned int irq_mask = 1 << get_gpio_index(gpio);
struct irq_desc *desc = irq_to_desc(irq);
u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
if (trigger)
_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
/* For level-triggered GPIOs, the clearing must be done after /* For level-triggered GPIOs, the clearing must be done after
* the HW source is cleared, thus after the handler has run */ * the HW source is cleared, thus after the handler has run */
...@@ -1350,9 +1401,49 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset) ...@@ -1350,9 +1401,49 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
return 0; return 0;
} }
static int gpio_is_input(struct gpio_bank *bank, int mask)
{
void __iomem *reg = bank->base;
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_IO_CNTL;
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_DIRECTION;
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_850:
reg += OMAP850_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_OE;
break;
}
return __raw_readl(reg) & mask;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset) static int gpio_get(struct gpio_chip *chip, unsigned offset)
{ {
return __omap_get_gpio_datain(chip->base + offset); struct gpio_bank *bank;
void __iomem *reg;
int gpio;
u32 mask;
gpio = chip->base + offset;
bank = get_gpio_bank(gpio);
reg = bank->base;
mask = 1 << get_gpio_index(gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
} }
static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
...@@ -1886,34 +1977,6 @@ arch_initcall(omap_gpio_sysinit); ...@@ -1886,34 +1977,6 @@ arch_initcall(omap_gpio_sysinit);
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
static int gpio_is_input(struct gpio_bank *bank, int mask)
{
void __iomem *reg = bank->base;
switch (bank->method) {
case METHOD_MPUIO:
reg += OMAP_MPUIO_IO_CNTL;
break;
case METHOD_GPIO_1510:
reg += OMAP1510_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_1610:
reg += OMAP1610_GPIO_DIRECTION;
break;
case METHOD_GPIO_730:
reg += OMAP730_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_850:
reg += OMAP850_GPIO_DIR_CONTROL;
break;
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_OE;
break;
}
return __raw_readl(reg) & mask;
}
static int dbg_gpio_show(struct seq_file *s, void *unused) static int dbg_gpio_show(struct seq_file *s, void *unused)
{ {
unsigned i, j, gpio; unsigned i, j, gpio;
......
...@@ -20,6 +20,8 @@ struct clockdomain; ...@@ -20,6 +20,8 @@ struct clockdomain;
struct clkops { struct clkops {
int (*enable)(struct clk *); int (*enable)(struct clk *);
void (*disable)(struct clk *); void (*disable)(struct clk *);
void (*find_idlest)(struct clk *, void __iomem **, u8 *);
void (*find_companion)(struct clk *, void __iomem **, u8 *);
}; };
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
......
...@@ -378,9 +378,6 @@ IS_OMAP_TYPE(3430, 0x3430) ...@@ -378,9 +378,6 @@ IS_OMAP_TYPE(3430, 0x3430)
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \ #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
cpu_is_omap44xx()) cpu_is_omap44xx())
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
defined(CONFIG_ARCH_OMAP4)
/* Various silicon revisions for omap2 */ /* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024 #define OMAP242X_CLASS 0x24200024
#define OMAP2420_REV_ES1_0 0x24200024 #define OMAP2420_REV_ES1_0 0x24200024
...@@ -436,5 +433,3 @@ IS_OMAP_TYPE(3430, 0x3430) ...@@ -436,5 +433,3 @@ IS_OMAP_TYPE(3430, 0x3430)
int omap_chip_is(struct omap_chip_id oci); int omap_chip_is(struct omap_chip_id oci);
void omap2_check_revision(void); void omap2_check_revision(void);
#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
...@@ -228,7 +228,8 @@ extern void omap1_map_common_io(void); ...@@ -228,7 +228,8 @@ extern void omap1_map_common_io(void);
extern void omap1_init_common_hw(void); extern void omap1_init_common_hw(void);
extern void omap2_map_common_io(void); extern void omap2_map_common_io(void);
extern void omap2_init_common_hw(struct omap_sdrc_params *sp); extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1);
#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
#define __arch_iounmap(v) omap_iounmap(v) #define __arch_iounmap(v) omap_iounmap(v)
......
...@@ -853,6 +853,10 @@ enum omap34xx_index { ...@@ -853,6 +853,10 @@ enum omap34xx_index {
AE5_34XX_GPIO143, AE5_34XX_GPIO143,
H19_34XX_GPIO164_OUT, H19_34XX_GPIO164_OUT,
J25_34XX_GPIO170, J25_34XX_GPIO170,
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
H16_34XX_SDRC_CKE0,
H17_34XX_SDRC_CKE1,
}; };
struct omap_mux_cfg { struct omap_mux_cfg {
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
u32 omap_prcm_get_reset_sources(void); u32 omap_prcm_get_reset_sources(void);
void omap_prcm_arch_reset(char mode); void omap_prcm_arch_reset(char mode);
int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name);
#endif #endif
......
...@@ -30,6 +30,10 @@ ...@@ -30,6 +30,10 @@
#define SDRC_ACTIM_CTRL_A_0 0x09c #define SDRC_ACTIM_CTRL_A_0 0x09c
#define SDRC_ACTIM_CTRL_B_0 0x0a0 #define SDRC_ACTIM_CTRL_B_0 0x0a0
#define SDRC_RFR_CTRL_0 0x0a4 #define SDRC_RFR_CTRL_0 0x0a4
#define SDRC_MR_1 0x0B4
#define SDRC_ACTIM_CTRL_A_1 0x0C4
#define SDRC_ACTIM_CTRL_B_1 0x0C8
#define SDRC_RFR_CTRL_1 0x0D4
/* /*
* These values represent the number of memory clock cycles between * These values represent the number of memory clock cycles between
...@@ -102,8 +106,11 @@ struct omap_sdrc_params { ...@@ -102,8 +106,11 @@ struct omap_sdrc_params {
u32 mr; u32 mr;
}; };
void __init omap2_sdrc_init(struct omap_sdrc_params *sp); void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r); struct omap_sdrc_params *sdrc_cs1);
int omap2_sdrc_get_params(unsigned long r,
struct omap_sdrc_params **sdrc_cs0,
struct omap_sdrc_params **sdrc_cs1);
#ifdef CONFIG_ARCH_OMAP2 #ifdef CONFIG_ARCH_OMAP2
......
...@@ -59,6 +59,7 @@ extern void omap_uart_check_wakeup(void); ...@@ -59,6 +59,7 @@ extern void omap_uart_check_wakeup(void);
extern void omap_uart_prepare_suspend(void); extern void omap_uart_prepare_suspend(void);
extern void omap_uart_prepare_idle(int num); extern void omap_uart_prepare_idle(int num);
extern void omap_uart_resume_idle(int num); extern void omap_uart_resume_idle(int num);
extern void omap_uart_enable_irqs(int enable);
#endif #endif
#endif #endif
...@@ -21,11 +21,12 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, ...@@ -21,11 +21,12 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type); u32 mem_type);
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, extern u32 omap3_configure_core_dpll(
u32 sdrc_actim_ctrla, u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_actim_ctrlb, u32 m2, u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 unlock_dll, u32 f, u32 sdrc_mr, u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 inc); u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
/* Do not use these */ /* Do not use these */
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl); extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
...@@ -59,12 +60,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, ...@@ -59,12 +60,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
u32 mem_type); u32 mem_type);
extern unsigned long omap243x_sram_reprogram_sdrc_sz; extern unsigned long omap243x_sram_reprogram_sdrc_sz;
extern u32 omap3_sram_configure_core_dpll(
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_actim_ctrla, u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrlb, u32 m2, u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 unlock_dll, u32 f, u32 sdrc_mr, u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 inc); u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
extern unsigned long omap3_sram_configure_core_dpll_sz; extern unsigned long omap3_sram_configure_core_dpll_sz;
#endif #endif
...@@ -44,9 +44,9 @@ ...@@ -44,9 +44,9 @@
#define OMAP2_SRAM_VA 0xe3000000 #define OMAP2_SRAM_VA 0xe3000000
#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800) #define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
#define OMAP3_SRAM_PA 0x40200000 #define OMAP3_SRAM_PA 0x40200000
#define OMAP3_SRAM_VA 0xd7000000 #define OMAP3_SRAM_VA 0xe3000000
#define OMAP3_SRAM_PUB_PA 0x40208000 #define OMAP3_SRAM_PUB_PA 0x40208000
#define OMAP3_SRAM_PUB_VA 0xd7008000 #define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
#define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/ #define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/
#define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/ #define OMAP4_SRAM_VA 0xd7000000 /*0xd70f0000*/
...@@ -373,20 +373,26 @@ static inline int omap243x_sram_init(void) ...@@ -373,20 +373,26 @@ static inline int omap243x_sram_init(void)
#ifdef CONFIG_ARCH_OMAP3 #ifdef CONFIG_ARCH_OMAP3
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl, static u32 (*_omap3_sram_configure_core_dpll)(
u32 sdrc_actim_ctrla, u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_actim_ctrlb, u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 m2, u32 unlock_dll, u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 f, u32 sdrc_mr, u32 inc); u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla, u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
u32 f, u32 sdrc_mr, u32 inc) u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
{ {
BUG_ON(!_omap3_sram_configure_core_dpll); BUG_ON(!_omap3_sram_configure_core_dpll);
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl, return _omap3_sram_configure_core_dpll(
sdrc_actim_ctrla, m2, unlock_dll, f, inc,
sdrc_actim_ctrlb, m2, sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
unlock_dll, f, sdrc_mr, inc); sdrc_actim_ctrl_b_0, sdrc_mr_0,
sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
sdrc_actim_ctrl_b_1, sdrc_mr_1);
} }
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */ /* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
......
...@@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) ...@@ -129,7 +129,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
/* calculate the MISCCR setting for the clock */ /* calculate the MISCCR setting for the clock */
if (parent == &clk_xtal) if (parent == &clk_mpll)
source = S3C2410_MISCCR_CLK0_MPLL; source = S3C2410_MISCCR_CLK0_MPLL;
else if (parent == &clk_upll) else if (parent == &clk_upll)
source = S3C2410_MISCCR_CLK0_UPLL; source = S3C2410_MISCCR_CLK0_UPLL;
......
...@@ -527,7 +527,7 @@ config SERIAL_S3C24A0 ...@@ -527,7 +527,7 @@ config SERIAL_S3C24A0
config SERIAL_S3C6400 config SERIAL_S3C6400
tristate "Samsung S3C6400/S3C6410 Serial port support" tristate "Samsung S3C6400/S3C6410 Serial port support"
depends on SERIAL_SAMSUNG && (CPU_S3C600 || CPU_S3C6410) depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410)
default y default y
help help
Serial port support for the Samsung S3C6400 and S3C6410 Serial port support for the Samsung S3C6400 and S3C6410
......
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