Commit 0fa4246e authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher

drm/amd/amdgpu: Add VMID to SRBM debugfs bank selection

Add 5 bits to the offset for SRBM selection to handle VMIDs.  Also
update the select_me_pipe_q() callback to also select VMID.
Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cf034477
...@@ -106,10 +106,10 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, ...@@ -106,10 +106,10 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
ssize_t result = 0; ssize_t result = 0;
int r; int r;
bool pm_pg_lock, use_bank, use_ring; bool pm_pg_lock, use_bank, use_ring;
unsigned instance_bank, sh_bank, se_bank, me, pipe, queue; unsigned instance_bank, sh_bank, se_bank, me, pipe, queue, vmid;
pm_pg_lock = use_bank = use_ring = false; pm_pg_lock = use_bank = use_ring = false;
instance_bank = sh_bank = se_bank = me = pipe = queue = 0; instance_bank = sh_bank = se_bank = me = pipe = queue = vmid = 0;
if (size & 0x3 || *pos & 0x3 || if (size & 0x3 || *pos & 0x3 ||
((*pos & (1ULL << 62)) && (*pos & (1ULL << 61)))) ((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
...@@ -135,6 +135,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, ...@@ -135,6 +135,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
me = (*pos & GENMASK_ULL(33, 24)) >> 24; me = (*pos & GENMASK_ULL(33, 24)) >> 24;
pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
queue = (*pos & GENMASK_ULL(53, 44)) >> 44; queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
vmid = (*pos & GENMASK_ULL(48, 45)) >> 54;
use_ring = 1; use_ring = 1;
} else { } else {
...@@ -152,7 +153,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, ...@@ -152,7 +153,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
sh_bank, instance_bank); sh_bank, instance_bank);
} else if (use_ring) { } else if (use_ring) {
mutex_lock(&adev->srbm_mutex); mutex_lock(&adev->srbm_mutex);
amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue); amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid);
} }
if (pm_pg_lock) if (pm_pg_lock)
...@@ -185,7 +186,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f, ...@@ -185,7 +186,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
mutex_unlock(&adev->grbm_idx_mutex); mutex_unlock(&adev->grbm_idx_mutex);
} else if (use_ring) { } else if (use_ring) {
amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0); amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex); mutex_unlock(&adev->srbm_mutex);
} }
......
...@@ -195,7 +195,7 @@ struct amdgpu_gfx_funcs { ...@@ -195,7 +195,7 @@ struct amdgpu_gfx_funcs {
uint32_t wave, uint32_t start, uint32_t size, uint32_t wave, uint32_t start, uint32_t size,
uint32_t *dst); uint32_t *dst);
void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
u32 queue); u32 queue, u32 vmid);
}; };
struct amdgpu_ngg_buf { struct amdgpu_ngg_buf {
...@@ -327,7 +327,7 @@ struct amdgpu_gfx { ...@@ -327,7 +327,7 @@ struct amdgpu_gfx {
#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q)) #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
/** /**
* amdgpu_gfx_create_bitmask - create a bitmask * amdgpu_gfx_create_bitmask - create a bitmask
......
...@@ -3043,7 +3043,7 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, ...@@ -3043,7 +3043,7 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
} }
static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q) u32 me, u32 pipe, u32 q, u32 vm)
{ {
DRM_INFO("Not implemented\n"); DRM_INFO("Not implemented\n");
} }
......
...@@ -4169,9 +4169,9 @@ static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, ...@@ -4169,9 +4169,9 @@ static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
} }
static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q) u32 me, u32 pipe, u32 q, u32 vm)
{ {
cik_srbm_select(adev, me, pipe, q, 0); cik_srbm_select(adev, me, pipe, q, vm);
} }
static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
......
...@@ -3436,9 +3436,9 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, ...@@ -3436,9 +3436,9 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
} }
static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q) u32 me, u32 pipe, u32 q, u32 vm)
{ {
vi_srbm_select(adev, me, pipe, q, 0); vi_srbm_select(adev, me, pipe, q, vm);
} }
static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
......
...@@ -1313,9 +1313,9 @@ static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, ...@@ -1313,9 +1313,9 @@ static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
} }
static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 q) u32 me, u32 pipe, u32 q, u32 vm)
{ {
soc15_grbm_select(adev, me, pipe, q, 0); soc15_grbm_select(adev, me, pipe, q, vm);
} }
static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment