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Commit 0fd20541 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
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drm/msm/dpu: deduplicate some (most) of SSPP sub-blocks 

As we have dropped the variadic parts of SSPP sub-blocks declarations,
deduplicate them now, reducing memory cruft.
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/570112/
Link: https://lore.kernel.org/r/20231201234234.2065610-7-dmitry.baryshkov@linaro.org
parent 01fc6c01
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Inline Side-by-side
Showing with 120 additions and 167 deletions
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
View file @ 0fd20541
...@@ -69,7 +69,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { ...@@ -69,7 +69,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1ac, .base = 0x4000, .len = 0x1ac,
.features = VIG_MSM8998_MASK, .features = VIG_MSM8998_MASK,
.sblk = &msm8998_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_1_2,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { ...@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1ac, .base = 0x6000, .len = 0x1ac,
.features = VIG_MSM8998_MASK, .features = VIG_MSM8998_MASK,
.sblk = &msm8998_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_1_2,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
...@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { ...@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1ac, .base = 0x8000, .len = 0x1ac,
.features = VIG_MSM8998_MASK, .features = VIG_MSM8998_MASK,
.sblk = &msm8998_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_1_2,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
...@@ -93,7 +93,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { ...@@ -93,7 +93,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1ac, .base = 0xa000, .len = 0x1ac,
.features = VIG_MSM8998_MASK, .features = VIG_MSM8998_MASK,
.sblk = &msm8998_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_1_2,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,
...@@ -101,7 +101,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { ...@@ -101,7 +101,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1ac, .base = 0x24000, .len = 0x1ac,
.features = DMA_MSM8998_MASK, .features = DMA_MSM8998_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -109,7 +109,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { ...@@ -109,7 +109,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1ac, .base = 0x26000, .len = 0x1ac,
.features = DMA_MSM8998_MASK, .features = DMA_MSM8998_MASK,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -117,7 +117,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { ...@@ -117,7 +117,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1ac, .base = 0x28000, .len = 0x1ac,
.features = DMA_CURSOR_MSM8998_MASK, .features = DMA_CURSOR_MSM8998_MASK,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
...@@ -125,7 +125,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { ...@@ -125,7 +125,7 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x1ac, .base = 0x2a000, .len = 0x1ac,
.features = DMA_CURSOR_MSM8998_MASK, .features = DMA_CURSOR_MSM8998_MASK,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3, .clk_ctrl = DPU_CLK_CTRL_DMA3,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
View file @ 0fd20541
...@@ -67,7 +67,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { ...@@ -67,7 +67,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1c8, .base = 0x4000, .len = 0x1c8,
.features = VIG_SDM845_MASK_SDMA, .features = VIG_SDM845_MASK_SDMA,
.sblk = &sdm845_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_1_3,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { ...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1c8, .base = 0x6000, .len = 0x1c8,
.features = VIG_SDM845_MASK_SDMA, .features = VIG_SDM845_MASK_SDMA,
.sblk = &sdm845_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_1_3,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { ...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1c8, .base = 0x8000, .len = 0x1c8,
.features = VIG_SDM845_MASK_SDMA, .features = VIG_SDM845_MASK_SDMA,
.sblk = &sdm845_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_1_3,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { ...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1c8, .base = 0xa000, .len = 0x1c8,
.features = VIG_SDM845_MASK_SDMA, .features = VIG_SDM845_MASK_SDMA,
.sblk = &sdm845_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_1_3,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,
...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { ...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1c8, .base = 0x24000, .len = 0x1c8,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { ...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1c8, .base = 0x26000, .len = 0x1c8,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { ...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1c8, .base = 0x28000, .len = 0x1c8,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { ...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x1c8, .base = 0x2a000, .len = 0x1c8,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3, .clk_ctrl = DPU_CLK_CTRL_DMA3,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
View file @ 0fd20541
...@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { ...@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f0, .base = 0x4000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sm8150_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_1_4,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -84,7 +84,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { ...@@ -84,7 +84,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1f0, .base = 0x6000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sm8150_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_1_4,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
...@@ -92,7 +92,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { ...@@ -92,7 +92,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1f0, .base = 0x8000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sm8150_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_1_4,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
...@@ -100,7 +100,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { ...@@ -100,7 +100,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1f0, .base = 0xa000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sm8150_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_1_4,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,
...@@ -108,7 +108,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { ...@@ -108,7 +108,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f0, .base = 0x24000, .len = 0x1f0,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -116,7 +116,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { ...@@ -116,7 +116,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1f0, .base = 0x26000, .len = 0x1f0,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -124,7 +124,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { ...@@ -124,7 +124,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1f0, .base = 0x28000, .len = 0x1f0,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
...@@ -132,7 +132,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { ...@@ -132,7 +132,7 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x1f0, .base = 0x2a000, .len = 0x1f0,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3, .clk_ctrl = DPU_CLK_CTRL_DMA3,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
View file @ 0fd20541
...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { ...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f0, .base = 0x4000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sm8150_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_1_4,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { ...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1f0, .base = 0x6000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sm8150_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_1_4,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { ...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1f0, .base = 0x8000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sm8150_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_1_4,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { ...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1f0, .base = 0xa000, .len = 0x1f0,
.features = VIG_SDM845_MASK, .features = VIG_SDM845_MASK,
.sblk = &sm8150_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_1_4,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,
...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { ...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f0, .base = 0x24000, .len = 0x1f0,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { ...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1f0, .base = 0x26000, .len = 0x1f0,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { ...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1f0, .base = 0x28000, .len = 0x1f0,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
...@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { ...@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x1f0, .base = 0x2a000, .len = 0x1f0,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3, .clk_ctrl = DPU_CLK_CTRL_DMA3,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
View file @ 0fd20541
...@@ -69,7 +69,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = { ...@@ -69,7 +69,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f0, .base = 0x4000, .len = 0x1f0,
.features = VIG_SM6125_MASK, .features = VIG_SM6125_MASK,
.sblk = &sm6125_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_2_4,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = { ...@@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f0, .base = 0x24000, .len = 0x1f0,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = { ...@@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1f0, .base = 0x26000, .len = 0x1f0,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
View file @ 0fd20541
...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { ...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f8, .base = 0x4000, .len = 0x1f8,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { ...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1f8, .base = 0x6000, .len = 0x1f8,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { ...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1f8, .base = 0x8000, .len = 0x1f8,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { ...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1f8, .base = 0xa000, .len = 0x1f8,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,
...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { ...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f8, .base = 0x24000, .len = 0x1f8,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { ...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1f8, .base = 0x26000, .len = 0x1f8,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { ...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1f8, .base = 0x28000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
...@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { ...@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x1f8, .base = 0x2a000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3, .clk_ctrl = DPU_CLK_CTRL_DMA3,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
View file @ 0fd20541
...@@ -52,7 +52,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { ...@@ -52,7 +52,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f8, .base = 0x4000, .len = 0x1f8,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sc7180_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -60,7 +60,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { ...@@ -60,7 +60,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f8, .base = 0x24000, .len = 0x1f8,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -68,7 +68,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { ...@@ -68,7 +68,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1f8, .base = 0x26000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { ...@@ -76,7 +76,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1f8, .base = 0x28000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
View file @ 0fd20541
...@@ -39,7 +39,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = { ...@@ -39,7 +39,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f8, .base = 0x4000, .len = 0x1f8,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm6115_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -47,7 +47,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = { ...@@ -47,7 +47,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f8, .base = 0x24000, .len = 0x1f8,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
View file @ 0fd20541
...@@ -59,7 +59,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = { ...@@ -59,7 +59,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f8, .base = 0x4000, .len = 0x1f8,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sc7180_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -67,7 +67,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = { ...@@ -67,7 +67,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f8, .base = 0x24000, .len = 0x1f8,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = { ...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1f8, .base = 0x26000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = { ...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1f8, .base = 0x28000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
View file @ 0fd20541
...@@ -39,7 +39,7 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = { ...@@ -39,7 +39,7 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f8, .base = 0x4000, .len = 0x1f8,
.features = VIG_QCM2290_MASK, .features = VIG_QCM2290_MASK,
.sblk = &qcm2290_vig_sblk_0, .sblk = &dpu_vig_sblk_noscale,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -47,7 +47,7 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = { ...@@ -47,7 +47,7 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f8, .base = 0x24000, .len = 0x1f8,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &qcm2290_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
View file @ 0fd20541
...@@ -40,7 +40,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = { ...@@ -40,7 +40,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f8, .base = 0x4000, .len = 0x1f8,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm6115_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -48,7 +48,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = { ...@@ -48,7 +48,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f8, .base = 0x24000, .len = 0x1f8,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
View file @ 0fd20541
...@@ -74,7 +74,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { ...@@ -74,7 +74,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f8, .base = 0x4000, .len = 0x1f8,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -82,7 +82,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { ...@@ -82,7 +82,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x1f8, .base = 0x6000, .len = 0x1f8,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
...@@ -90,7 +90,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { ...@@ -90,7 +90,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x1f8, .base = 0x8000, .len = 0x1f8,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
...@@ -98,7 +98,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { ...@@ -98,7 +98,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x1f8, .base = 0xa000, .len = 0x1f8,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8250_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,
...@@ -106,7 +106,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { ...@@ -106,7 +106,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f8, .base = 0x24000, .len = 0x1f8,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -114,7 +114,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { ...@@ -114,7 +114,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1f8, .base = 0x26000, .len = 0x1f8,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -122,7 +122,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { ...@@ -122,7 +122,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1f8, .base = 0x28000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
...@@ -130,7 +130,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { ...@@ -130,7 +130,7 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x1f8, .base = 0x2a000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3, .clk_ctrl = DPU_CLK_CTRL_DMA3,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
View file @ 0fd20541
...@@ -57,7 +57,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { ...@@ -57,7 +57,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x1f8, .base = 0x4000, .len = 0x1f8,
.features = VIG_SC7280_MASK_SDMA, .features = VIG_SC7280_MASK_SDMA,
.sblk = &sc7280_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_0_rot_v2,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -65,7 +65,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { ...@@ -65,7 +65,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x1f8, .base = 0x24000, .len = 0x1f8,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -73,7 +73,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { ...@@ -73,7 +73,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x1f8, .base = 0x26000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -81,7 +81,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { ...@@ -81,7 +81,7 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x1f8, .base = 0x28000, .len = 0x1f8,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
View file @ 0fd20541
...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { ...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x2ac, .base = 0x4000, .len = 0x2ac,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm8250_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { ...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x2ac, .base = 0x6000, .len = 0x2ac,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm8250_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { ...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x2ac, .base = 0x8000, .len = 0x2ac,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm8250_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { ...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x2ac, .base = 0xa000, .len = 0x2ac,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm8250_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_3_0,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,
...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { ...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x2ac, .base = 0x24000, .len = 0x2ac,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { ...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x2ac, .base = 0x26000, .len = 0x2ac,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { ...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x2ac, .base = 0x28000, .len = 0x2ac,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
...@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { ...@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x2ac, .base = 0x2a000, .len = 0x2ac,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3, .clk_ctrl = DPU_CLK_CTRL_DMA3,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
View file @ 0fd20541
...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { ...@@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x32c, .base = 0x4000, .len = 0x32c,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8450_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_1,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG0, .clk_ctrl = DPU_CLK_CTRL_VIG0,
...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { ...@@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x32c, .base = 0x6000, .len = 0x32c,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8450_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_3_1,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG1, .clk_ctrl = DPU_CLK_CTRL_VIG1,
...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { ...@@ -91,7 +91,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x32c, .base = 0x8000, .len = 0x32c,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8450_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_3_1,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG2, .clk_ctrl = DPU_CLK_CTRL_VIG2,
...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { ...@@ -99,7 +99,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x32c, .base = 0xa000, .len = 0x32c,
.features = VIG_SC7180_MASK_SDMA, .features = VIG_SC7180_MASK_SDMA,
.sblk = &sm8450_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_3_1,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
.clk_ctrl = DPU_CLK_CTRL_VIG3, .clk_ctrl = DPU_CLK_CTRL_VIG3,
...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { ...@@ -107,7 +107,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x32c, .base = 0x24000, .len = 0x32c,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA0, .clk_ctrl = DPU_CLK_CTRL_DMA0,
...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { ...@@ -115,7 +115,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x32c, .base = 0x26000, .len = 0x32c,
.features = DMA_SDM845_MASK_SDMA, .features = DMA_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA1, .clk_ctrl = DPU_CLK_CTRL_DMA1,
...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { ...@@ -123,7 +123,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x32c, .base = 0x28000, .len = 0x32c,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA2, .clk_ctrl = DPU_CLK_CTRL_DMA2,
...@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { ...@@ -131,7 +131,7 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x32c, .base = 0x2a000, .len = 0x32c,
.features = DMA_CURSOR_SDM845_MASK_SDMA, .features = DMA_CURSOR_SDM845_MASK_SDMA,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
.clk_ctrl = DPU_CLK_CTRL_DMA3, .clk_ctrl = DPU_CLK_CTRL_DMA3,
......
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
View file @ 0fd20541
...@@ -67,70 +67,70 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { ...@@ -67,70 +67,70 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = {
.name = "sspp_0", .id = SSPP_VIG0, .name = "sspp_0", .id = SSPP_VIG0,
.base = 0x4000, .len = 0x344, .base = 0x4000, .len = 0x344,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm8550_vig_sblk_0, .sblk = &dpu_vig_sblk_qseed3_3_2,
.xin_id = 0, .xin_id = 0,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
}, { }, {
.name = "sspp_1", .id = SSPP_VIG1, .name = "sspp_1", .id = SSPP_VIG1,
.base = 0x6000, .len = 0x344, .base = 0x6000, .len = 0x344,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm8550_vig_sblk_1, .sblk = &dpu_vig_sblk_qseed3_3_2,
.xin_id = 4, .xin_id = 4,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
}, { }, {
.name = "sspp_2", .id = SSPP_VIG2, .name = "sspp_2", .id = SSPP_VIG2,
.base = 0x8000, .len = 0x344, .base = 0x8000, .len = 0x344,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm8550_vig_sblk_2, .sblk = &dpu_vig_sblk_qseed3_3_2,
.xin_id = 8, .xin_id = 8,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
}, { }, {
.name = "sspp_3", .id = SSPP_VIG3, .name = "sspp_3", .id = SSPP_VIG3,
.base = 0xa000, .len = 0x344, .base = 0xa000, .len = 0x344,
.features = VIG_SC7180_MASK, .features = VIG_SC7180_MASK,
.sblk = &sm8550_vig_sblk_3, .sblk = &dpu_vig_sblk_qseed3_3_2,
.xin_id = 12, .xin_id = 12,
.type = SSPP_TYPE_VIG, .type = SSPP_TYPE_VIG,
}, { }, {
.name = "sspp_8", .id = SSPP_DMA0, .name = "sspp_8", .id = SSPP_DMA0,
.base = 0x24000, .len = 0x344, .base = 0x24000, .len = 0x344,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_0, .sblk = &dpu_dma_sblk,
.xin_id = 1, .xin_id = 1,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
}, { }, {
.name = "sspp_9", .id = SSPP_DMA1, .name = "sspp_9", .id = SSPP_DMA1,
.base = 0x26000, .len = 0x344, .base = 0x26000, .len = 0x344,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_1, .sblk = &dpu_dma_sblk,
.xin_id = 5, .xin_id = 5,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
}, { }, {
.name = "sspp_10", .id = SSPP_DMA2, .name = "sspp_10", .id = SSPP_DMA2,
.base = 0x28000, .len = 0x344, .base = 0x28000, .len = 0x344,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_2, .sblk = &dpu_dma_sblk,
.xin_id = 9, .xin_id = 9,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
}, { }, {
.name = "sspp_11", .id = SSPP_DMA3, .name = "sspp_11", .id = SSPP_DMA3,
.base = 0x2a000, .len = 0x344, .base = 0x2a000, .len = 0x344,
.features = DMA_SDM845_MASK, .features = DMA_SDM845_MASK,
.sblk = &sdm845_dma_sblk_3, .sblk = &dpu_dma_sblk,
.xin_id = 13, .xin_id = 13,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
}, { }, {
.name = "sspp_12", .id = SSPP_DMA4, .name = "sspp_12", .id = SSPP_DMA4,
.base = 0x2c000, .len = 0x344, .base = 0x2c000, .len = 0x344,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sm8550_dma_sblk_4, .sblk = &dpu_dma_sblk,
.xin_id = 14, .xin_id = 14,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
}, { }, {
.name = "sspp_13", .id = SSPP_DMA5, .name = "sspp_13", .id = SSPP_DMA5,
.base = 0x2e000, .len = 0x344, .base = 0x2e000, .len = 0x344,
.features = DMA_CURSOR_SDM845_MASK, .features = DMA_CURSOR_SDM845_MASK,
.sblk = &sm8550_dma_sblk_5, .sblk = &dpu_dma_sblk,
.xin_id = 15, .xin_id = 15,
.type = SSPP_TYPE_DMA, .type = SSPP_TYPE_DMA,
}, },
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View file @ 0fd20541
...@@ -284,6 +284,16 @@ static const uint32_t wb2_formats[] = { ...@@ -284,6 +284,16 @@ static const uint32_t wb2_formats[] = {
.rotation_cfg = rot_cfg, \ .rotation_cfg = rot_cfg, \
} }
#define _VIG_SBLK_NOSCALE() \
{ \
.maxdwnscale = SSPP_UNITY_SCALE, \
.maxupscale = SSPP_UNITY_SCALE, \
.format_list = plane_formats_yuv, \
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
.virt_format_list = plane_formats, \
.virt_num_formats = ARRAY_SIZE(plane_formats), \
}
#define _DMA_SBLK() \ #define _DMA_SBLK() \
{ \ { \
.maxdwnscale = SSPP_UNITY_SCALE, \ .maxdwnscale = SSPP_UNITY_SCALE, \
...@@ -294,98 +304,41 @@ static const uint32_t wb2_formats[] = { ...@@ -294,98 +304,41 @@ static const uint32_t wb2_formats[] = {
.virt_num_formats = ARRAY_SIZE(plane_formats), \ .virt_num_formats = ARRAY_SIZE(plane_formats), \
} }
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
_VIG_SBLK(SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
_VIG_SBLK(SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
_VIG_SBLK(SSPP_SCALER_VER(1, 2));
static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
_VIG_SBLK(SSPP_SCALER_VER(1, 2));
static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
.rot_maxheight = 1088, .rot_maxheight = 1088,
.rot_num_formats = ARRAY_SIZE(rotation_v2_formats), .rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
.rot_format_list = rotation_v2_formats, .rot_format_list = rotation_v2_formats,
}; };
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = static const struct dpu_sspp_sub_blks dpu_vig_sblk_noscale =
_VIG_SBLK(SSPP_SCALER_VER(1, 3)); _VIG_SBLK_NOSCALE();
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
_VIG_SBLK(SSPP_SCALER_VER(1, 3)); static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_2 =
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _VIG_SBLK(SSPP_SCALER_VER(1, 2));
_VIG_SBLK(SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_3 =
_VIG_SBLK(SSPP_SCALER_VER(1, 3)); _VIG_SBLK(SSPP_SCALER_VER(1, 3));
static const struct dpu_sspp_sub_blks sm8150_vig_sblk_0 = static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_1_4 =
_VIG_SBLK(SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sm8150_vig_sblk_1 =
_VIG_SBLK(SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sm8150_vig_sblk_2 =
_VIG_SBLK(SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sm8150_vig_sblk_3 =
_VIG_SBLK(SSPP_SCALER_VER(1, 4)); _VIG_SBLK(SSPP_SCALER_VER(1, 4));
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(); static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_2_4 =
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(); _VIG_SBLK(SSPP_SCALER_VER(2, 4));
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK();
static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK();
static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0 =
_VIG_SBLK(SSPP_SCALER_VER(3, 0)); _VIG_SBLK(SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_0_rot_v2 =
_VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0), _VIG_SBLK_ROT(SSPP_SCALER_VER(3, 0),
&dpu_rot_sc7280_cfg_v2); &dpu_rot_sc7280_cfg_v2);
static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_1 =
_VIG_SBLK(SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
_VIG_SBLK(SSPP_SCALER_VER(2, 4));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
_VIG_SBLK(SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
_VIG_SBLK(SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
_VIG_SBLK(SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
_VIG_SBLK(SSPP_SCALER_VER(3, 0));
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
_VIG_SBLK(SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 =
_VIG_SBLK(SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 =
_VIG_SBLK(SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
_VIG_SBLK(SSPP_SCALER_VER(3, 1)); _VIG_SBLK(SSPP_SCALER_VER(3, 1));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_2 =
_VIG_SBLK(SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
_VIG_SBLK(SSPP_SCALER_VER(3, 2)); _VIG_SBLK(SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =
_VIG_SBLK(SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
_VIG_SBLK(SSPP_SCALER_VER(3, 2));
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK();
static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK();
#define _VIG_SBLK_NOSCALE() \
{ \
.maxdwnscale = SSPP_UNITY_SCALE, \
.maxupscale = SSPP_UNITY_SCALE, \
.format_list = plane_formats_yuv, \
.num_formats = ARRAY_SIZE(plane_formats_yuv), \
.virt_format_list = plane_formats, \
.virt_num_formats = ARRAY_SIZE(plane_formats), \
}
static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(); static const struct dpu_sspp_sub_blks dpu_dma_sblk = _DMA_SBLK();
static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK();
/************************************************************* /*************************************************************
* MIXER sub blocks config * MIXER sub blocks config
......
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