Commit 10d83730 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Don't wait for page flips if there was GPU reset

If a GPU reset occurs while a page flip has been submitted to the ring,
the flip will never complete once the ring has been reset.

The GPU reset can be detected by sampling the reset_counter before the
flip is submitted, and then while waiting for the flip, the sampled
counter is compared with the current reset_counter value.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
[danvet: Move the reset_counter assignment to an earlier place in
common code as discussed on the mailing list.]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60140Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3d56e2d6
...@@ -2868,10 +2868,12 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) ...@@ -2868,10 +2868,12 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev; struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
unsigned long flags; unsigned long flags;
bool pending; bool pending;
if (i915_reset_in_progress(&dev_priv->gpu_error)) if (i915_reset_in_progress(&dev_priv->gpu_error) ||
intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
return false; return false;
spin_lock_irqsave(&dev->event_lock, flags); spin_lock_irqsave(&dev->event_lock, flags);
...@@ -7250,6 +7252,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, ...@@ -7250,6 +7252,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
work->enable_stall_check = true; work->enable_stall_check = true;
atomic_inc(&intel_crtc->unpin_work_count); atomic_inc(&intel_crtc->unpin_work_count);
intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
if (ret) if (ret)
......
...@@ -235,6 +235,9 @@ struct intel_crtc { ...@@ -235,6 +235,9 @@ struct intel_crtc {
/* We can share PLLs across outputs if the timings match */ /* We can share PLLs across outputs if the timings match */
struct intel_pch_pll *pch_pll; struct intel_pch_pll *pch_pll;
uint32_t ddi_pll_sel; uint32_t ddi_pll_sel;
/* reset counter value when the last flip was submitted */
unsigned int reset_counter;
}; };
struct intel_plane { struct intel_plane {
......
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