ARM: dts: stm32: Enable crc1 and cryp1 where applicable on DHSOM

Enable the CRC accelerator on all STM32MP15xx DHSOM based systems
and CRYP accelerator on all STM32MP15x[CF] DHSOM based systems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts

@@ -20,6 +20,10 @@ / {
 		     "st,stm32mp153";
 };
 
+&cryp1 {
+	status = "okay";
+};
+
 &m_can1 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&m_can1_pins_a>;

arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts

@@ -20,6 +20,10 @@ / {
 		     "st,stm32mp157";
 };
 
+&cryp1 {
+	status = "okay";
+};
+
 &m_can1 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&m_can1_pins_a>;

arch/arm/boot/dts/stm32mp157c-dhcom-picoitx.dts

@@ -20,6 +20,10 @@ / {
 		     "st,stm32mp157";
 };
 
+&cryp1 {
+	status = "okay";
+};
+
 &m_can1 {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&m_can1_pins_a>;

arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi

@@ -92,6 +92,10 @@ adc2: adc@100 {
 	};
 };
 
+&crc1 {
+	status = "okay";
+};
+
 &dac {
 	pinctrl-names = "default";
 	pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;

arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi

@@ -21,6 +21,10 @@ memory@c0000000 {
 	};
 };
 
+&crc1 {
+	status = "okay";
+};
+
 &dts {
 	status = "okay";
 };